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2016 International Symposium on Integrated Circuits (ISIC)最新文献

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A high speed pipeline ADC with 78-dB SFDR in 0.18 um BiCMOS 在0.18 um BiCMOS中具有78 db SFDR的高速流水线ADC
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829725
Jie Sun, Jianhui Wu
{"title":"A high speed pipeline ADC with 78-dB SFDR in 0.18 um BiCMOS","authors":"Jie Sun, Jianhui Wu","doi":"10.1109/ISICIR.2016.7829725","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829725","url":null,"abstract":"a 12 bit 300 MS/s ADC with 78-dB SFDR in 0.18um SiGe BiCMOS process is presented. Such ADC consumes 170 mW under the supply of 1.9V. To improve the power efficiency and settling accuracy, the ADC employs a novel residue amplifier (RA). In addition, it includes a clock buffer to generate the low jitter clock from the signal source outside the chip. Reference buffer is fully integrated to provide stable differential reference voltages with little noise. A low power comparator with fast response and modest offset is also presented. The simulation results show that with Nyquist input, the SFDR is 78 dB and the ENOB is 10.9 bit.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122045470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Safety evaluation based on virtual prototypes: Fault injection with multi-level processor models 基于虚拟原型的安全评价:多级处理器模型的故障注入
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829710
Daniel Mueller-Gritschneder, Marc Greim, Ulf Schlichtmann
{"title":"Safety evaluation based on virtual prototypes: Fault injection with multi-level processor models","authors":"Daniel Mueller-Gritschneder, Marc Greim, Ulf Schlichtmann","doi":"10.1109/ISICIR.2016.7829710","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829710","url":null,"abstract":"This abstract gave an overview of fault injection into embedded processors at VP level. The ETISS processor simulator is integrated into a SystemC/TLM VP and extended by plugins. A plugin for switching to RTL level simulation for accurate simulation of soft errors was described. Experimental results for a control system and the OpenRISC processor were given.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126508078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 10 to 170 GHz distributed amplifier using 130-nm SiGe HBTs 采用130纳米SiGe hts的10至170 GHz分布式放大器
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829679
Yihu Li, W. Goh, Hailin Tang, Haitao Liu, Xiaodong Deng, Y. Xiong
{"title":"A 10 to 170 GHz distributed amplifier using 130-nm SiGe HBTs","authors":"Yihu Li, W. Goh, Hailin Tang, Haitao Liu, Xiaodong Deng, Y. Xiong","doi":"10.1109/ISICIR.2016.7829679","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829679","url":null,"abstract":"This paper presents an ultra-broadband distributed amplifier (DA). The amplifying cell utilizes the three-level stacked transistor structure. Loss compensation techniques are used to broaden the operating bandwidth with layout considerations. 130 nm SiGe HBTs are used to fabricate the proposed design, the total chip area occupied is 1.3mm×0.7mm including the bonding pads. With on-chip RF choking inductors and DC blocking capacitors, the designed DA achieves a band width of 10 to 170 GHz, with the average gain of 19 dB. The total power consumption of the DA is 560 mW with a power supply voltage of 4.5 V.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130231976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
High voltage high efficiency UWB pulse generator for precision localization wireless sensor network 用于无线传感器网络精确定位的高压高效率超宽带脉冲发生器
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829696
M. Ansari, C. Law
{"title":"High voltage high efficiency UWB pulse generator for precision localization wireless sensor network","authors":"M. Ansari, C. Law","doi":"10.1109/ISICIR.2016.7829696","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829696","url":null,"abstract":"A high voltage, high efficiency ultra-wideband (UWB) Gaussian pulse generator for the precision localization of mobile objects in wireless sensor network system is presented. The proposed microwave monolithic integrated circuit (mmic) for the UWB pulse generator has peak output power of 25.7dBm with 0.9 mW total power consumption at 0.5 MHz pulse repetition frequency. The proposed pulse generator efficiency is 19.9%. The high output power is achieved by overcoming the breakdown phenomena of the transistor for higher output voltage by using two transistors in series. The 2µm HBT ADS model is used for the circuit simulation. The power spectrum of the generated pulse fully utilizes the FCC peak power limit spectrum mask. The generated UWB pulse is centered at 4.2 GHz with peak-to-peak voltage of 12.2 V into a 50 ohms load. The generated pulse envelop has full width at half maxima of 0.85 nsec.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122444675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A low-power digital design of all digital PLL for 2.4G wireless communication applications 用于2.4G无线通信应用的全数字锁相环的低功耗数字设计
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829674
Bin Zhao, D. Yan
{"title":"A low-power digital design of all digital PLL for 2.4G wireless communication applications","authors":"Bin Zhao, D. Yan","doi":"10.1109/ISICIR.2016.7829674","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829674","url":null,"abstract":"a low-power all-digital PLL (ADPLL) is proposed for the 2.4G wireless communication applications. A new scheme is proposed for noise reduction of the quantization noise that is caused by the metastability between reference clock and the DCO output clock (CKV). The ADPLL is designed and fabricated in 0.65µm CMOS process, the whole digital block area is 0.065 mm2(include TDC).","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121224947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and verification methodologies for Smart Battery Cells 智能电池的设计和验证方法
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829706
S. Steinhorst
{"title":"Design and verification methodologies for Smart Battery Cells","authors":"S. Steinhorst","doi":"10.1109/ISICIR.2016.7829706","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829706","url":null,"abstract":"Lithium-Ion (Li-Ion) battery packs are continuously gaining in importance in many energy storage applications such as electric vehicles and smart energy grids. Such battery packs require advanced Battery Management Systems (BMSs), which are contributions from the embedded systems and integrated circuits domain. The BMS monitors and controls the battery cells in a pack and ensures the functionality, efficiency, safety and reliability of the pack. Conventional BMS designs employ a centralized controller architecture for the whole battery pack. Recently, Smart Battery Cells have been proposed which enable a complete decentralization of the BMS. In Smart Battery Cells, each cell is equipped with a Cell Management Unit (CMU) which individually manages the cell it is attached to. By communication with other Smart Battery Cells, the pack-level functionality of the BMS is provided in a distributed fashion. While this architecture provides many benefits such as scalability, minimal integration effort and increased functional safety, existing design and verification methodologies can neither be applied on hardware nor on software level. Consequently, this contribution will discuss how such methodologies for Smart Battery Cells could be developed and points out which further research contributions are needed. For this purpose, we address modeling and simulation of cyberphysical aspects on all abstraction levels and illustrate how verification approaches can be introduced to this new field of application.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127607441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Digitally-controlled H-bridge DC-DC converter for micropower PV energy harvesting system 用于微功率光伏能量收集系统的数字控制h桥DC-DC变换器
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829681
A. Bui, Zhekai Xiao, L. Siek
{"title":"Digitally-controlled H-bridge DC-DC converter for micropower PV energy harvesting system","authors":"A. Bui, Zhekai Xiao, L. Siek","doi":"10.1109/ISICIR.2016.7829681","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829681","url":null,"abstract":"This paper presents a micro-power photovoltaic (PV) harvesting system. A H-bridge configuration DC-DC converter is designed to harvest PV energy and deliver energy to applications of Internet of Thing (IOT). The main converter consists of a single inductor with two inputs and two outputs. It regulates a constant 1V output voltage for several applications such as sensors and signal transmitters. The surplus energy is stored in a rechargeable battery. The battery also serves as a secondary input source to provide energy to the output load in heavy-load condition. Due to the limited energy of the system, the power consumption of the power system is optimized by several techniques. A perturb-and-observe maximum power point tracker (MPPT) is implemented to maximize the power extracted from the PV harvester. Pulse-width modulation (PWM) and pulse-frequency modulation (PFM) are used to regulate the output voltage. The controller is designed mainly in digital and free of power-hungry circuits. The proposed converter occupies an area of 1.44mm2. The estimated peak power efficiency is 84% while driving 3–10µA load current.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131224212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
ESD protection design for high-speed circuits in nanoscale CMOS process 纳米级CMOS工艺中高速电路的ESD保护设计
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829726
Chun-Yu Lin, Rong-Kun Chang
{"title":"ESD protection design for high-speed circuits in nanoscale CMOS process","authors":"Chun-Yu Lin, Rong-Kun Chang","doi":"10.1109/ISICIR.2016.7829726","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829726","url":null,"abstract":"To protect the high-speed integrated circuits from electrostatic discharge (ESD) damages, the ESD protection design of inductor-assisted silicon-controlled rectifier (LASCR) is investigated in this work. Compared with the conventional ESD protection design of dual-diode, the LASCR has better high-speed performances and higher ESD robustness. Therefore, the LASCR is very suitable for high-speed applications.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116839144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A review of audio Class D amplifiers 音频D类放大器综述
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829693
Y. Kang, T. Ge, Huiqiao He, J. Chang
{"title":"A review of audio Class D amplifiers","authors":"Y. Kang, T. Ge, Huiqiao He, J. Chang","doi":"10.1109/ISICIR.2016.7829693","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829693","url":null,"abstract":"Class D amplifiers (CDAs) are increasingly ubiquitous as the audio power amplifier (loudspeaker driver) in audio devices due to their significantly higher power-efficiency compared to their linear counterparts. In this paper, a comprehensive review on the design of audio Class D amplifiers is provided, including a comparison of commonly used design architectures/modulation schemes. The key design parameters, including Total Harmonic Distortion, Power Supply Rejection Ratio, Intermodulation Distortion, are discussed and the design tradeoffs between these parameters delineated.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117237575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Accelerating OpenSSL's ECC with low cost reconfigurable hardware 用低成本的可重构硬件加速OpenSSL的ECC
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829684
Debapriya Basu Roy, Shubham Agrawal, C. Rebeiro, Debdeep Mukhopadhyay
{"title":"Accelerating OpenSSL's ECC with low cost reconfigurable hardware","authors":"Debapriya Basu Roy, Shubham Agrawal, C. Rebeiro, Debdeep Mukhopadhyay","doi":"10.1109/ISICIR.2016.7829684","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829684","url":null,"abstract":"Security protocols based on elliptic curves are gradually becoming the standard for a wide range of applications. However, the intensive mathematical computations involved in elliptic curve cryptography (ECC), create performance bottlenecks for a number of applications involving web servers, cloud computing infrastructures, and data centers. Side-by-side, software implementations of ECC are plagued with several implementation specific attacks. Reconfigurable hardware accelerators for ECC can solve both these problems. It can provide the necessary speeds to match the performance requirements of the applications, and can also provide an isolated environment, which can prevent several known attacks. In this paper, we demonstrate a reconfigurable hardware accelerator for OpenSSL's implementation of ECC, and show how a low cost hardware platform is sufficient to double performance.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114345448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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