A high speed pipeline ADC with 78-dB SFDR in 0.18 um BiCMOS

Abstract

a 12 bit 300 MS/s ADC with 78-dB SFDR in 0.18um SiGe BiCMOS process is presented. Such ADC consumes 170 mW under the supply of 1.9V. To improve the power efficiency and settling accuracy, the ADC employs a novel residue amplifier (RA). In addition, it includes a clock buffer to generate the low jitter clock from the signal source outside the chip. Reference buffer is fully integrated to provide stable differential reference voltages with little noise. A low power comparator with fast response and modest offset is also presented. The simulation results show that with Nyquist input, the SFDR is 78 dB and the ENOB is 10.9 bit.