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2016 International Symposium on Integrated Circuits (ISIC)最新文献

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A three bit second order audio band delta sigma modulator with 98.2dB SQNR 具有98.2dB SQNR的3位二阶音频波段δ σ调制器
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829750
Henrik Felding, Linus Hellman, Siyu Tan, Markus Törmänen
{"title":"A three bit second order audio band delta sigma modulator with 98.2dB SQNR","authors":"Henrik Felding, Linus Hellman, Siyu Tan, Markus Törmänen","doi":"10.1109/ISICIR.2016.7829750","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829750","url":null,"abstract":"A three bit second order delta sigma modulator for audio applications implemented in 130nm CMOS technology is presented. The modulator features two integrators, a flash quantizer and two current steering DACs. In order to minimize the effect of delays in the DACs, excessive loop delay (ELD) compensation is utilized. Using an oversampling ratio (OSR) of 80, the design consumes 2.8mW and achieves a simulated signal to quantization noise ratio (SQNR) of 98.2dB. The chip area is minimized by decreasing the number of digital to analog converters (DACs) by using the concept of partial integration. The compact design occupies an active core area of 630µm × 600µm.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114731863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A regulated voltage multiplier for passive RFID Tag 一种用于无源RFID标签的稳压倍增器
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829735
J. Jia, M. Ho, K. Leung, Jianping Guo
{"title":"A regulated voltage multiplier for passive RFID Tag","authors":"J. Jia, M. Ho, K. Leung, Jianping Guo","doi":"10.1109/ISICIR.2016.7829735","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829735","url":null,"abstract":"A regulated voltage multiplier (VM) for ultra-high-frequency (UHF) passive RFID Tag is proposed and presented in this paper. The proposed UHF VM can be reconfigured with the different series and parallel combinations. The proposed UHF VM with voltage regulation is realized in a standard 180-nm CMOS technology. Experimental results show that a regulated voltage of 1.23 V is generated under load current of 55.9 µA and the maximum power-conversion efficiency reaches 35%. Moreover, the presented analysis is proven by the well-matched calculated and measured results.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127393642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An inductorless transimpedance amplifier design for 10 Gb/s optical communication using 0.18-µm CMOS 基于0.18µm CMOS的10gb /s光通信无电感跨阻放大器设计
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829701
L. Samuel, Tan Yung Sern, T. B. Kumar, Y. K. Seng, L. Zhichao, Yu Xiaopeng
{"title":"An inductorless transimpedance amplifier design for 10 Gb/s optical communication using 0.18-µm CMOS","authors":"L. Samuel, Tan Yung Sern, T. B. Kumar, Y. K. Seng, L. Zhichao, Yu Xiaopeng","doi":"10.1109/ISICIR.2016.7829701","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829701","url":null,"abstract":"This paper presents a novel inductorless transimpedance amplifier (TIA) design using Global Foundaries 0.18-µm CMOS technology suitable for high speed optical communication. A modified-RGC preamplifier stage (M-RGC) is used to lower input impedance through cascode and parallel PMOS transistor techniques for wideband operation. The amplifier stage used common source amplifiers to increase the gain and the third-order interleaving feedback technique to increase the bandwidth. The proposed TIA has a transimpedance gain of 59.5 dBΩ with bandwidth of 6.16 GHz and a power consumption of 21.2 mW (core power = 17.5 mW) for VDD = 1.8 V.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121489974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Stack effect and logic restructuring on high Fan-in FinFETs logic gates 高扇入finfet逻辑门的堆叠效应与逻辑重构
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829722
S. Jayapal, Janani Sainath Sigundey, Yipin Wu, EricT Tsai
{"title":"Stack effect and logic restructuring on high Fan-in FinFETs logic gates","authors":"S. Jayapal, Janani Sainath Sigundey, Yipin Wu, EricT Tsai","doi":"10.1109/ISICIR.2016.7829722","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829722","url":null,"abstract":"In this paper we discuss the properties of FinFETs with regards to device width quantization, stack effect, logic restructuring, in contrast to the conventional planar MOSFETs. We analyzed stack effect and proposed a device sizing and logic restructuring co-design approach and found that there is no stack effect among FinFETs. We experimented both proposed and conventional logic method using industrial 7nm FinFET and achieved an area reduction by 37.5%, power reduced by 57% for the proposed method when compared to the conventional logic method. But this comes with a delay penalty of 42.2%. Since no stack effect can be observed with FinFETs we have also proposed high Fan-in gates structure and achieved a reduction in input capacitance, which was not considered in planar MOSFETs due to high input capacitance. Also, we proposed a design flow for FinFETs.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134293831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack 差分功率分析攻击下异步逻辑QDI单元方法的安全性分析
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829712
Weng-Geng Ho, Ali Akbar Pammu, Nan Liu, K. Z. L. Ne, Kwen-Siong Chong, B. Gwee
{"title":"Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack","authors":"Weng-Geng Ho, Ali Akbar Pammu, Nan Liu, K. Z. L. Ne, Kwen-Siong Chong, B. Gwee","doi":"10.1109/ISICIR.2016.7829712","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829712","url":null,"abstract":"We report a security analysis of the asynchronous-logic (async) quasi-delay-insensitive (QDI) Weak-Conditioned Half-Buffer (WCHB) cell approach against the side-channel differential power analysis (DPA) attack. When compared to the synchronous-logic (sync) standard cell approach, the WCHB cell approach is more power-balanced during the logic switching due to the unique features as follows. First, the WCHB cell approach embodies dual-rail data-encoding scheme, featuring more balanced power dissipation for different output transitions. Second, the WCHB cell approach embodies a power-constant input detector that validate the input-completeness, featuring more balanced power dissipation for different input combination. Based on 65nm CMOS process, the standard and WCHB cell approaches are simulated for 7 library cells, and compared in terms of the normalized energy deviation (NED) and normalized standard deviation (NSD). Nonetheless, the WCHB cell approach features 62% lower NED and 69% lower NSD than the standard cell approach.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133454372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A compact 6-bit phase shifter in 0.35 µm SiGe BiCMOS technology 紧凑的6位移相器，采用0.35µm SiGe BiCMOS技术
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829685
Zou Pei, Kaixue Ma, Shouxian Mou
{"title":"A compact 6-bit phase shifter in 0.35 µm SiGe BiCMOS technology","authors":"Zou Pei, Kaixue Ma, Shouxian Mou","doi":"10.1109/ISICIR.2016.7829685","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829685","url":null,"abstract":"This paper presents a compact 14–18 GHz 6-bit digital phase shifter based on 0.35-µm SiGe BiCOMS technology. Three different topologies are adopted to achieve the desired phase shift with low insertion loss, accurate phase shifting and small parasitic amplitude modulation. The simulated performance of all 64 states of the phase shifter demonstrates an insertion loss of 9±0.9 dB and a RMS phase error <4° with P<inf>1dB</inf> better than 11dBm. The input return loss and output return loss are better than −12 dB and −13.5dB over the 14–18 GHz frequency range respectively. And the chip size of this phase shifter is only 0.79×0.42 mm<sup>2</sup> excluding PADs.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132883771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 0.13µm CMOS full wave active rectifier with comparators for implanted medical devices 带有比较器的0.13µm CMOS全波有源整流器，用于植入医疗设备
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829677
Joao R. C. Louzada, L. Zoccal, R. Moreno, T. Pimenta
{"title":"A 0.13µm CMOS full wave active rectifier with comparators for implanted medical devices","authors":"Joao R. C. Louzada, L. Zoccal, R. Moreno, T. Pimenta","doi":"10.1109/ISICIR.2016.7829677","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829677","url":null,"abstract":"This paper presents a full wave active rectifier for biological implanted devices using a new original comparator to reduce the rectifier transistors reverse current. The rectifier was designed in 0.13µm CMOS process and it can deliver 1.09Vdc when receive a minimum signal of 1.2Vac. It achieves a power conversion efficiency of 81% when working at 13.56MHz Scientific and Medical (ISM) band.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134265580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A digitally controlled embedded SMPS with 2.3V to 5.5V input voltage for mobile SoCs 一种数字控制的嵌入式SMPS，输入电压为2.3V至5.5V，用于移动soc
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829709
Queenie Le, Deyu Chen, Daryl Cher, David Ho, Iulia Mirea, Rex Wong, Ricky Setiawan
{"title":"A digitally controlled embedded SMPS with 2.3V to 5.5V input voltage for mobile SoCs","authors":"Queenie Le, Deyu Chen, Daryl Cher, David Ho, Iulia Mirea, Rex Wong, Ricky Setiawan","doi":"10.1109/ISICIR.2016.7829709","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829709","url":null,"abstract":"The design of a 40 nm CMOS technology embedded switched-mode power supply (SMPS) for low-power mobile silicon-on-chip (SoC) is presented. The embedded SMPS operates directly from a Li-Ion battery capable of a wide input voltage range of 2.3 to 5.5V while the maximum voltage rating of the transistors used is 2.75V. This is achieved using integrated low-power voltage regulators and a novel dip compensation scheme. In addition, the SMPS is designed to include PWM and PFM modes to achieve high power efficiency over a wide load current range. To take advantage of the advanced 40 nm process, the PWM controller is implemented digitally. The digital controller, consisting of a successive approximation (SAR) ADC, digital compensation filter, and digital sigma delta PWM, is implemented to minimize silicon area and achieve fast transient response. The SMPS switches at 4.5 MHz and has peak efficiency of 83%, delivering a load of 240 mW when converting from 3.6V to 1.2V. It is capable of delivering a maximum power of 960 mW.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127177356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Capacitive charge pump gain-stage with source follower buffers for pipelined SAR ADCs 带源从动器缓冲器的电容式电荷泵增益级，用于流水线SAR adc
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829747
Kairang Chen, A. Alvandpour
{"title":"Capacitive charge pump gain-stage with source follower buffers for pipelined SAR ADCs","authors":"Kairang Chen, A. Alvandpour","doi":"10.1109/ISICIR.2016.7829747","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829747","url":null,"abstract":"Aiming to alleviate operational transconductance amplifiers (OTA), this paper describes the design of a capacitive charge pump (CCP) gain-stage for a two-stage pipelined SAR ADCs suitable for low-power sensors. An analog buffer is inevitable to prevent the charge sharing between the capacitive stages. In this work a simple source follower has been used as the analog buffer, showing sufficient linearity and significant power reduction compared to earlier work where a unity-gain OTA was used. To verify the solution, a CCP gain-stage with source follower has been implemented in design of a 14-bit two-stage pipelined SAR ADC in 0.18 µm CMOS. Detailed circuit simulations show that the ADC achieves a SNDR of 83.0 dB while consuming 1.8 µW at a sampling frequency of 10 kHz.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129201648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Automotive security state of the art and future challenges 汽车安全技术现状与未来挑战
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829737
Bernhard Jungk
{"title":"Automotive security state of the art and future challenges","authors":"Bernhard Jungk","doi":"10.1109/ISICIR.2016.7829737","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829737","url":null,"abstract":"In the last 20 years, most vehicles have seen a large increase in complexity of the electronic and software systems, e.g. the number of electronic control units (ECUs) increased to over 70 in many cars and connectivity to the Internet or over Bluetooth is possible. In combination, the increased complexity and a large attack surface due to the connectivity makes it necessary to investigate the security of each ECU as well as the overall vehicle architecture. Most of the security countermeasures that are implemented to date or will be implemented in the future require some kind of hardware support. This paper identifies which security mechanisms are already implemented, and which should be introduced in the future. It further discusses which parts of each mechanism require special hardware support.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124530959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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