{"title":"用于2.4G无线通信应用的全数字锁相环的低功耗数字设计","authors":"Bin Zhao, D. Yan","doi":"10.1109/ISICIR.2016.7829674","DOIUrl":null,"url":null,"abstract":"a low-power all-digital PLL (ADPLL) is proposed for the 2.4G wireless communication applications. A new scheme is proposed for noise reduction of the quantization noise that is caused by the metastability between reference clock and the DCO output clock (CKV). The ADPLL is designed and fabricated in 0.65µm CMOS process, the whole digital block area is 0.065 mm2(include TDC).","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A low-power digital design of all digital PLL for 2.4G wireless communication applications\",\"authors\":\"Bin Zhao, D. Yan\",\"doi\":\"10.1109/ISICIR.2016.7829674\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"a low-power all-digital PLL (ADPLL) is proposed for the 2.4G wireless communication applications. A new scheme is proposed for noise reduction of the quantization noise that is caused by the metastability between reference clock and the DCO output clock (CKV). The ADPLL is designed and fabricated in 0.65µm CMOS process, the whole digital block area is 0.065 mm2(include TDC).\",\"PeriodicalId\":159343,\"journal\":{\"name\":\"2016 International Symposium on Integrated Circuits (ISIC)\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International Symposium on Integrated Circuits (ISIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISICIR.2016.7829674\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Symposium on Integrated Circuits (ISIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISICIR.2016.7829674","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low-power digital design of all digital PLL for 2.4G wireless communication applications
a low-power all-digital PLL (ADPLL) is proposed for the 2.4G wireless communication applications. A new scheme is proposed for noise reduction of the quantization noise that is caused by the metastability between reference clock and the DCO output clock (CKV). The ADPLL is designed and fabricated in 0.65µm CMOS process, the whole digital block area is 0.065 mm2(include TDC).