基于虚拟原型的安全评价:多级处理器模型的故障注入

2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI:10.1109/ISICIR.2016.7829710

Daniel Mueller-Gritschneder, Marc Greim, Ulf Schlichtmann

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引用次数: 2

摘要

本文概述了VP级嵌入式处理器的故障注入。ETISS处理器模拟器集成到SystemC/TLM VP中，并通过插件进行扩展。介绍了一种切换到RTL级仿真的插件，以实现对软误差的精确仿真。给出了控制系统和OpenRISC处理器的实验结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Safety evaluation based on virtual prototypes: Fault injection with multi-level processor models

This abstract gave an overview of fault injection into embedded processors at VP level. The ETISS processor simulator is integrated into a SystemC/TLM VP and extended by plugins. A plugin for switching to RTL level simulation for accurate simulation of soft errors was described. Experimental results for a control system and the OpenRISC processor were given.

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2016 International Symposium on Integrated Circuits (ISIC)

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