A low-power digital design of all digital PLL for 2.4G wireless communication applications

Abstract

a low-power all-digital PLL (ADPLL) is proposed for the 2.4G wireless communication applications. A new scheme is proposed for noise reduction of the quantization noise that is caused by the metastability between reference clock and the DCO output clock (CKV). The ADPLL is designed and fabricated in 0.65µm CMOS process, the whole digital block area is 0.065 mm2(include TDC).