Boa-Hua Yu, Kaixue Ma, F. Meng, Bharatha Kumar Thangarasu, K. Yeo
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DC-50 GHz low loss switch matrix design in high resistivity trap-rich SOI
This paper presents low insertion loss, high isolation, ultra wideband (DC to 50 GHz) 2 × 2 switch matrix in a 300mm 0.13 µ m high substrate resistivity trap-rich SOI. The switches are designed by using a series-shunt-series configuration with input and output matching networks. The designed switches achieve a 1.8 dB of low insertion loss and a high isolation of 38 dB up to 50 GHz. 1dB-compression point of designed switches are larger than 19 dBm from DC to 50 GHz. The active chip area of designed 2 × 2 switch matrix is only 0.28 × 0.21 mm2.
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