2023 IEEE International Reliability Physics Symposium (IRPS)最新文献_第6页

Insights into device and material origins and physical mechanisms behind cross temperature in 3D NAND 深入了解器件和材料起源以及3D NAND中交叉温度背后的物理机制

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10117898

M. Pešić, Bastien Beltrando, Tommaso Rollo, C. Zambelli, A. Padovani, R. Micheloni, R. Maji, Lisa Enman, M. Saly, Yang Ho Bae, Jung Bae Kim, D. Yim, L. Larcher

引用次数: 0

A New Methodology to Precisely Induce Wake-Up for Reliability Assessment of Ferroelectric Devices 一种用于铁电器件可靠性评估的精确唤醒方法

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10117723

Tiang Teck Tan, Yu-Yun Wang, J. Tan, Tian-Li Wu, N. Raghavan, K. Pey

{"title":"A New Methodology to Precisely Induce Wake-Up for Reliability Assessment of Ferroelectric Devices","authors":"Tiang Teck Tan, Yu-Yun Wang, J. Tan, Tian-Li Wu, N. Raghavan, K. Pey","doi":"10.1109/IRPS48203.2023.10117723","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117723","url":null,"abstract":"Studies on ferroelectric (FE) device degradation are performed on “woken up” devices. The process of waking up a device is typically done by applying a logarithmically increasing number of pulsed, alternating bipolar switching voltage cycles. However, this method has low resolution in precisely achieving the wake-up state, resulting in ambiguity in the current stage of the life cycle of the device. Furthermore, ferroelectric device performance depends heavily on the spatio-temporal distribution of defects in the device stack, which are very different in the wake-up and fatigue phases of the life cycle. The standard bipolar pulsed stressing scheme as well as asymmetric device structure further complicate the analysis of the effects of voltage stressing on defect drift and subsequent device degradation. Here, we propose a new stressing methodology leveraging on an alternating stress-sense scheme using CVS/RVS and positive-up-negative-down (PUND) waveforms to better control the extent of wake-up in the device. Wake-up and the associated changes to the spatio-temporal mapping of the charged defect concentrations can be more confidently ascertained using the proposed methodology, thereby enabling better understanding of the reliability physics governing wake-up and fatigue for FE devices in the future for lifetime prediction from accelerated life tests.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124580008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Localized thermal effects in Gate-all-around devices 栅极全能器件的局部热效应

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10117903

C. Landon, Lei Jiang, D. Pantuso, I. Meric, K. Komeyli, J. Hicks, Daniel Schroeder

引用次数: 1

Reliability of InGaZnO Transparent ReRAM with Optically Active Pt-Nanodisks 具有光活性pt纳米盘的InGaZnO透明ReRAM的可靠性

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10118092

Kavita Vishwakarma, Rishabh Kishore, Suman Gora, Mandeep Jangra, Arnab Datta

引用次数: 0

Reliability Assessment of 3nm GAA Logic Technology Featuring Multi-Bridge-Channel FETs 多桥道场效应管3nm GAA逻辑技术的可靠性评估

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10117953

S. Kim, Hyerim Park, Eunyu Choi, Young Han Kim, Dahyub Kim, H. Shim, Shin-Young Chung, Paul Jung

{"title":"Reliability Assessment of 3nm GAA Logic Technology Featuring Multi-Bridge-Channel FETs","authors":"S. Kim, Hyerim Park, Eunyu Choi, Young Han Kim, Dahyub Kim, H. Shim, Shin-Young Chung, Paul Jung","doi":"10.1109/IRPS48203.2023.10117953","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117953","url":null,"abstract":"In this paper, we report reliability assessment of the Multi-Bridge-Channel FET (MBCFET) adopted 3nm gate all around (GAA) logic technology in comparison with the 4 and 8nm FinFET logic technologies. A notable improvement on negative bias temperature instability (NBTI) of MBCFET is observed thanks to {100} dominance. Gate oxide time-dependent-dielectric-breakdown (TDDB) of the 3nm MBCFETs is comparable to that of the 4nm and 8nm FinFETs. Self-heat decoupled hot-carrier-injection (HCI) is similar to that of the 4nm FinFETs. Reduced conductance maximum (Gm, max) indicates that HCI degradation of the 3nm MBCFETs is dominated by interface damage mechanism. Middle-of-the-line (MOL) TDDB Weibull distribution shows that the 3nm MBCFETs have shorter time-to-failure (TTF) due to reduced lateral distance from gate to diffusion contact than other FinFET logic technologies. Due to an adoption of self-aligned-contact (SAC), the 3nm MBCFETs have similar behavior on MOL breakdown voltage (Vbd) at various diffusion contact misalignment to the 4nm FinFETs. The 3nm MBCFETs show antenna immunity up to 3x antenna ratio. Lastly, thermal cycle (TC) results indicate that the 3nm GAA logic technology has little lattice-related defects.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127562651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Impact of Gate Stack Thermal Budget on NBTI Reliability in Gate-All-Around Nanosheet P-type Devices 栅极堆叠热收支对栅极全能纳米片p型器件NBTI可靠性的影响

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10117828

Huimei Zhou, Miaomiao Wang, N. Loubet, A. Gaul, Y. Sulehria

引用次数: 0

Unveiling Retention Physical Mechanism of Ge-rich GST ePCM Technology 揭示富ge GST ePCM技术保留物理机制

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10118155

L. Laurin, M. Baldo, E. Petroni, G. Samanni, Lorenzo Turconi, A. Motta, M. Borghi, A. Serafini, D. Codegoni, M. Scuderi, S. Ran, A. Claverie, D. Ielmini, R. Annunziata, A. Redaelli

引用次数: 0

Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited) 相变记忆漂移对模拟内存中计算深度学习推理能量效率和精度的影响(特邀)

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10117874

M. Frank, Ning Li, M. Rasch, Shubham Jain, Ching-Tzu Chen, R. Muralidhar, Jin P. Han, V. Narayanan, T. Philip, K. Brew, A. Simon, Iqbal Saraf, N. Saulnier, I. Boybat, Stanisław Woźniak, A. Sebastian, P. Narayanan, C. Mackin, An Chen, H. Tsai, G. Burr

{"title":"Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited)","authors":"M. Frank, Ning Li, M. Rasch, Shubham Jain, Ching-Tzu Chen, R. Muralidhar, Jin P. Han, V. Narayanan, T. Philip, K. Brew, A. Simon, Iqbal Saraf, N. Saulnier, I. Boybat, Stanisław Woźniak, A. Sebastian, P. Narayanan, C. Mackin, An Chen, H. Tsai, G. Burr","doi":"10.1109/IRPS48203.2023.10117874","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117874","url":null,"abstract":"Among the emerging approaches for deep learning acceleration, compute-in-memory (CIM) in crossbar arrays, in conjunction with optimized digital computation and communication, is attractive for achieving high execution speeds and energy efficiency. Analog phase-change memory (PCM) is particularly promising for this purpose. However, resistance typically drifts, which can degrade deep learning accuracy over time. Herein, we first discuss drift and noise mitigation by integrating projection liners into analog mushroom-type PCM devices, as well as tradeoffs with dynamic range. We then study their impact on inference accuracy for the Transformer-based language model BERT. We find that accuracy loss after extended drift can be minimal with an optimized mapping of weights to cells comprising two pairs of liner PCM devices of varying significance. Finally, we address the impact of drift on energy consumption during inference through a combination of drift, circuit, and architecture simulations. For a range of typical drift coefficients, we show that the peak vector-matrix multiplication (VMM) energy efficiency of a recently proposed heterogeneous CIM accelerator in 14 nm technology can increase by 3% to 15% over the course of one day to ten years. For convolutional neural network (CNN), long short-term memory (LSTM) and Transformer benchmarks, the increase in sustained energy efficiency remains below 10%, being greatest for models dominated by analog computation. Longer VMM integration times increase the energy impact of drift.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125172000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Advanced Methods of Detecting Physical Damages in Packaging and BEOL Interconnects 包装和BEOL互连中物理损伤检测的先进方法

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10117720

J. Mendoza, Jimmy-Bao Le, C. Kim, H. Lin

{"title":"Advanced Methods of Detecting Physical Damages in Packaging and BEOL Interconnects","authors":"J. Mendoza, Jimmy-Bao Le, C. Kim, H. Lin","doi":"10.1109/IRPS48203.2023.10117720","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117720","url":null,"abstract":"This paper reports new methods of detecting damages and failures in packaging interconnects in fully packaged devices with sufficient sensitivity and selectivity for damages in interconnects. Exploration on various electrical methods leads to the conclusion that a few electrical measurement techniques, especially one using a low frequency AC signal, may provide effective mechanism of detecting the damages under interest. Impedance and derived parameters such as capacitance and inductance show sensitivity to silicon-package-interaction damages, with satisfactory immunity to parasitic signals present in fully assembled/packaged test chips such as the probe/pad contact resistance and stray capacitance from various sources. Two highlighting examples based on the “open circuit test pattern” are introduced in this paper to demonstrate the effectiveness of developed methods. The first is the damage detection in the high resistance open circuit pattern, which consists of small metal serpentines strategically placed on the failure prone places in BEOL of Si chip. Small damage develop in the metal serpentine makes the circuits to produce LC resonance-like signals useful in detecting presence of damage and its location. The second is the impedance method sensitive to the damage/failure in low resistance open circuit pattern like solder interconnects. The method measures the impedance as a function of frequency and design to detects the crack and/or void trapped/developed at the solder joints mainly using the skin effect in AC resistance. The technique is with its own limitations but can enable effective characterization of damages in package interconnects.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124497218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High- Temperature PBTI in Trench-Gate Vertical GaN Power MOSFETs: Role of Border and Semiconductor Traps 沟栅垂直GaN功率mosfet中的高温PBTI:边界和半导体陷阱的作用

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10117667

D. Favero, A. Cavaliere, C. D. Santi, M. Borga, W. G. Filho, K. Geens, B. Bakeroot, S. Decoutere, G. Meneghesso, E. Zanoni, M. Meneghini

引用次数: 0