Impact of Gate Stack Thermal Budget on NBTI Reliability in Gate-All-Around Nanosheet P-type Devices

NBTI impact from gate stack thermal budget in Gate-All-Around Nanosheet (GAA NS) architecture is presented in this work. Varying effects of post high-k deposition anneal (PDA), spike-anneal (SA), and laser annealing (LSA) are studied in terms of the NBTI-induced threshold voltage shifts. It is observed that the NBTI, gate leakage, and mobility are significantly modulated by interfacial layer (IL) formation and Nitrogen (N) concentration from varying annealing and thermal budget. Optimized thermal process is identified to improve NBTI reliability without mobility and gate leakage degradation.