Advanced Methods of Detecting Physical Damages in Packaging and BEOL Interconnects

Abstract

This paper reports new methods of detecting damages and failures in packaging interconnects in fully packaged devices with sufficient sensitivity and selectivity for damages in interconnects. Exploration on various electrical methods leads to the conclusion that a few electrical measurement techniques, especially one using a low frequency AC signal, may provide effective mechanism of detecting the damages under interest. Impedance and derived parameters such as capacitance and inductance show sensitivity to silicon-package-interaction damages, with satisfactory immunity to parasitic signals present in fully assembled/packaged test chips such as the probe/pad contact resistance and stray capacitance from various sources. Two highlighting examples based on the “open circuit test pattern” are introduced in this paper to demonstrate the effectiveness of developed methods. The first is the damage detection in the high resistance open circuit pattern, which consists of small metal serpentines strategically placed on the failure prone places in BEOL of Si chip. Small damage develop in the metal serpentine makes the circuits to produce LC resonance-like signals useful in detecting presence of damage and its location. The second is the impedance method sensitive to the damage/failure in low resistance open circuit pattern like solder interconnects. The method measures the impedance as a function of frequency and design to detects the crack and/or void trapped/developed at the solder joints mainly using the skin effect in AC resistance. The technique is with its own limitations but can enable effective characterization of damages in package interconnects.