Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.最新文献

筛选
英文 中文
The enabling solution of Cu/low-k planarization technology 铜/低钾平化技术的使能方案
Y. Wada, I. Noji, I. Kobata, T. Kohama, A. Fukunaga, M. Tsujimura
{"title":"The enabling solution of Cu/low-k planarization technology","authors":"Y. Wada, I. Noji, I. Kobata, T. Kohama, A. Fukunaga, M. Tsujimura","doi":"10.1109/IITC.2005.1499951","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499951","url":null,"abstract":"The electro-chemical polishing in DI water (\"ECP-DI\" technology) and the advanced CMP technology (\"mC/sup 2/\") are introduced, as a new noble low down-force planarization technology. Each process is developed for the Cu bulk polishing step of Cu/ultra low-k devices. The ECP-DI is governed by Faraday's law, and that principle involves 'di-plating' of only the part coming into contact with the ion exchange film. Advanced CMP is a process which is not governed by Preston's law, but by the dissolution law.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132131505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
BEOL process integration technology for 45 nm node porous low-k/copper interconnects 45纳米节点多孔低k/铜互连的BEOL工艺集成技术
N. Matsunaga, N. Nakamura, K. Higashi, H. Yamaguchi, T. Watanabe, K. Akiyama, S. Nakao, K. Fujita, H. Miyajima, S. Omoto, A. Sakata, T. Katata, Y. Kagawa, H. Kawashima, Y. Enomoto, T. Hasegawa, H. Shibata
{"title":"BEOL process integration technology for 45 nm node porous low-k/copper interconnects","authors":"N. Matsunaga, N. Nakamura, K. Higashi, H. Yamaguchi, T. Watanabe, K. Akiyama, S. Nakao, K. Fujita, H. Miyajima, S. Omoto, A. Sakata, T. Katata, Y. Kagawa, H. Kawashima, Y. Enomoto, T. Hasegawa, H. Shibata","doi":"10.1109/IITC.2005.1499903","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499903","url":null,"abstract":"Highly reliable BEOL integration technology with porous low-k (k=2.3) was realized by development focusing on plasma damage control and moisture control. A hybrid dielectric scheme with damage resistant porous low-k films and buffer film was applied in view of its inherent advantages for realizing reliable porous low-k integration. A metallization process was developed from the viewpoint of suppressing morphology and adhesion degradation of barrier metal by oxidation. A dummy wiring pattern was also adopted to remove moisture absorbed in porous low-k films. Stress-migration and electromigration satisfying practical reliability were obtained with via size of 75 nm for the first time by utilizing all possible measures for reducing the damage and the moisture.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"370 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116324477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
New insight into stress induced voiding mechanism in Cu interconnects Cu互连中应力诱导空化机制的新认识
Sun-jung Lee, Soo-Geun Lee, B. Suh, Hong-jae Shin, N. Lee, Ho-Kyu Kang, G. Suh
{"title":"New insight into stress induced voiding mechanism in Cu interconnects","authors":"Sun-jung Lee, Soo-Geun Lee, B. Suh, Hong-jae Shin, N. Lee, Ho-Kyu Kang, G. Suh","doi":"10.1109/IITC.2005.1499943","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499943","url":null,"abstract":"An effective method was used for the failure analysis of stress induced voids. Instead of conventional vertical inspection, the lower wide copper surface connected to the via was investigated after removing the passivation layer and upper copper layer. Many voids were observed at the grain boundary area, regardless of via location. According to the step by step inspection of that surface, many small voids were generated at the grain boundary area after dielectric barrier deposition, even before an HTS (high temperature storage) test, and some of the voids were grown after HTS, preferentially at the grain boundary corners. This result implies that unlucky landing of via over the grain boundary area would be the main cause of stress induced void under the via.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129463770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Optimization of signal propagation performances in interconnects of the 45 nm node by exhaustive analysis of the technological parameters impact 通过对工艺参数影响的详尽分析,优化45nm节点互连中的信号传播性能
A. Farcy, O. Cueto, B. Blampey, V. Arnal, L. Gosset, W. Besling, S. Chhun, T. Lacrevaz, C. Bermond, B. Fléchet, O. Rousire, F. de Crécy, G. Angénieux, J. Torres
{"title":"Optimization of signal propagation performances in interconnects of the 45 nm node by exhaustive analysis of the technological parameters impact","authors":"A. Farcy, O. Cueto, B. Blampey, V. Arnal, L. Gosset, W. Besling, S. Chhun, T. Lacrevaz, C. Bermond, B. Fléchet, O. Rousire, F. de Crécy, G. Angénieux, J. Torres","doi":"10.1109/IITC.2005.1499929","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499929","url":null,"abstract":"Due to the continuous shrink of technology dimensions, parasitic propagation delay time and crosstalk at interconnect levels increasingly affect overall circuit performances. New materials, processes and architectures are now required to improve BEOL performances. A rigorous high-frequency electromagnetic approach including the scattering effects on Cu line resistance was developed for coupled narrow interconnects to analyze the actual benefits of these innovations for different signal types covering application range from logic to I/O. Effects of advanced metallization (ALD thin barriers), low-k insulators (porous ULKs, low-k barriers), and innovative architectures (hybrid stacks, air gaps, self-aligned barriers) on signal propagation performance were quantified, resulting in an effective process selection for the 45 nm technological node and below.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117299020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Extendibility of PVD barrier/seed for BEOL Cu metallization 用于BEOL铜金属化的PVD屏障/种子的可扩展性
C. Yang, D. Edelstein, L. Clevenger, A. Cowley, J. Gill, K. Chanda, A. Simon, T. Dalton, B. Agarwala, E. Cooney, D. Nguyen, T. Spooner, A. Stamper
{"title":"Extendibility of PVD barrier/seed for BEOL Cu metallization","authors":"C. Yang, D. Edelstein, L. Clevenger, A. Cowley, J. Gill, K. Chanda, A. Simon, T. Dalton, B. Agarwala, E. Cooney, D. Nguyen, T. Spooner, A. Stamper","doi":"10.1109/IITC.2005.1499954","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499954","url":null,"abstract":"The paper describes a new physical vapor deposition (PVD) metallization scheme that shows a better extendibility for future technology nodes as compared to the conventional scheme. In addition to reducing the thicknesses of both the diffusion barrier and the copper seed layer (Yang, C.-C. et al., MRS Adv. Metallization Conf., p.213, 2004), this new scheme also features a sacrificial process (also called barrier-first process) (Alers, G., IEEE Int. Interconnect Technology Conf., 2003), a via-punch through process (Edelstein, D. et al., IEEE Int. Reliability Physics Symp., p.316, 2004; Kuma, N. et al., MRS Adv. Metallization Conf, p.247, 2004) and a simultaneous preclean with a metal neutral deposition process (Yang et al., US Patent 6,784,105, 2004; Uzoh, C. et al., US Patents 5,930,669, 1999; 5,933,753, 1999; 6,429,519, 2002). Significant metal line and via contact resistance decrease was observed with equal or better reliability. The impact of a sputter etch integration scheme on electrical yield and reliability is also reported. The new sputter scheme decreases contact resistance at the via/interconnect interface and can offset the one resulting from dimension scaling and thus extends PVD metallization usefulness for future technologies.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"70 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123468565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Impact of Cu barrier dielectrics upon stress-induced voiding of dual-damascene copper interconnects 铜势垒介质对双砷铜互连应力致空化的影响
K. Ishikawa, H. Shimazu, T. Oshima, J. Noguchi, T. Tamaru, H. Aoki, T. Ando, T. Iwasaki, T. Saito
{"title":"Impact of Cu barrier dielectrics upon stress-induced voiding of dual-damascene copper interconnects","authors":"K. Ishikawa, H. Shimazu, T. Oshima, J. Noguchi, T. Tamaru, H. Aoki, T. Ando, T. Iwasaki, T. Saito","doi":"10.1109/IITC.2005.1499916","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499916","url":null,"abstract":"In this paper, we discuss the stress-induced voiding (SIV) in dual-damascene Cu interconnects. To relax the Cu stress and its gradient, we focused on the Cu barrier dielectrics. The SIV of Cu interconnects was successfully suppressed by using SiC film as a Cu barrier dielectric. The finite element method (FEM) and the molecular dynamics (MD) analysis revealed the stress distribution and its effects on the void growth.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124536121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Effect of CoWP cap thickness on via yield and reliability for Cu interconnects with CoWP-only cap process cop帽厚度对纯cop帽工艺铜互连通孔率和可靠性的影响
J. Gambino, J. Wynne, S. Smith, S. Mongeon, P. Pokrinchak, D. Meatyard
{"title":"Effect of CoWP cap thickness on via yield and reliability for Cu interconnects with CoWP-only cap process","authors":"J. Gambino, J. Wynne, S. Smith, S. Mongeon, P. Pokrinchak, D. Meatyard","doi":"10.1109/IITC.2005.1499944","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499944","url":null,"abstract":"Via resistance and stress migration lifetime were characterized for a CoWP-only cap process (i.e. no dielectric cap) and a CoWP+SiN cap process. For the CoWP-only process, the via resistance and stress migration lifetime depended on the CoWP thickness. In order to achieve a tightly distributed via resistance and long stress migration lifetime, the data suggests that the CoWP must be sufficiently thick to protect the Cu during the via etch and strip processes.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124140953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Current and future challenges of DRAM metallization DRAM金属化的当前和未来挑战
D. Weber, A. Thies, U. Kahler, M. Lepper, R. Schutz
{"title":"Current and future challenges of DRAM metallization","authors":"D. Weber, A. Thies, U. Kahler, M. Lepper, R. Schutz","doi":"10.1109/IITC.2005.1499974","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499974","url":null,"abstract":"The challenges and requirements of current and future DRAM interconnect schemes are described. In contrast to most logic metallization development and manufacturing, these requirements include tight pitches in array area, low resistance in the chip periphery, contacts with landing area smaller than the contacts themselves, AlCu fill into high aspect ratio contacts, continued drive toward lower capacitances and, perhaps above all, low cost.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132980872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Barrier layer effects on electromigration reliability of Cu/low k interconnects 阻挡层对铜/低钾互连电迁移可靠性的影响
X. Lu, J. Pyun, B. Li, N. Henis, K. Neuman, K. Pfeifer, P. Ho
{"title":"Barrier layer effects on electromigration reliability of Cu/low k interconnects","authors":"X. Lu, J. Pyun, B. Li, N. Henis, K. Neuman, K. Pfeifer, P. Ho","doi":"10.1109/IITC.2005.1499914","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499914","url":null,"abstract":"The effects of barrier thickness scaling and process changes on electromigration (EM) reliability were investigated for Cu/porous low k interconnects. Both EM strong mode lifetime and critical length-current density product (jL)/sub c/ were found to be almost independent of the Ta barrier thickness. The results can be accounted for by considering the structural confinement effect based on the effective modulus B. With reducing barrier thickness, early failures emerged in multi-link test structures degrading EM lifetime and the critical (jL)/sub c/ product. A non-optimized barrier deposition process can significantly alter the void formation site, leading to a reduction in EM lifetime and (jL)/sub c/ product. In this case, failure analyses by FIB and TEM have identified defects related to Cu out-diffusion to induce lifetime degradation and line shorting.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"28 20","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131839339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Design rules for improving predictability of on-chip antenna characteristics in the presence of other metal structures 在存在其他金属结构的情况下,提高片上天线特性可预测性的设计规则
E. Seok, K. O. Kenneth
{"title":"Design rules for improving predictability of on-chip antenna characteristics in the presence of other metal structures","authors":"E. Seok, K. O. Kenneth","doi":"10.1109/IITC.2005.1499949","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499949","url":null,"abstract":"The impact of on-chip metal interference structures, such as a power grid, local clock trees and data lines, on on-chip antenna performance has been investigated. A power grid significantly changes the input impedance and the phase of S/sub 12/ for an antenna pair, and reduces |S/sub 12/|. However, the addition of extra metal structures in the presence of a power grid has a much attenuated impact on the antenna characteristics. The reduction in |S/sub 12/| can be traded for increased predictability of antenna performance. Exploiting this observation, a set of design rules for increasing the predictability of on-chip antenna characteristics is proposed.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134582356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信