C. Yang, D. Edelstein, L. Clevenger, A. Cowley, J. Gill, K. Chanda, A. Simon, T. Dalton, B. Agarwala, E. Cooney, D. Nguyen, T. Spooner, A. Stamper
{"title":"用于BEOL铜金属化的PVD屏障/种子的可扩展性","authors":"C. Yang, D. Edelstein, L. Clevenger, A. Cowley, J. Gill, K. Chanda, A. Simon, T. Dalton, B. Agarwala, E. Cooney, D. Nguyen, T. Spooner, A. Stamper","doi":"10.1109/IITC.2005.1499954","DOIUrl":null,"url":null,"abstract":"The paper describes a new physical vapor deposition (PVD) metallization scheme that shows a better extendibility for future technology nodes as compared to the conventional scheme. In addition to reducing the thicknesses of both the diffusion barrier and the copper seed layer (Yang, C.-C. et al., MRS Adv. Metallization Conf., p.213, 2004), this new scheme also features a sacrificial process (also called barrier-first process) (Alers, G., IEEE Int. Interconnect Technology Conf., 2003), a via-punch through process (Edelstein, D. et al., IEEE Int. Reliability Physics Symp., p.316, 2004; Kuma, N. et al., MRS Adv. Metallization Conf, p.247, 2004) and a simultaneous preclean with a metal neutral deposition process (Yang et al., US Patent 6,784,105, 2004; Uzoh, C. et al., US Patents 5,930,669, 1999; 5,933,753, 1999; 6,429,519, 2002). Significant metal line and via contact resistance decrease was observed with equal or better reliability. The impact of a sputter etch integration scheme on electrical yield and reliability is also reported. The new sputter scheme decreases contact resistance at the via/interconnect interface and can offset the one resulting from dimension scaling and thus extends PVD metallization usefulness for future technologies.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"70 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Extendibility of PVD barrier/seed for BEOL Cu metallization\",\"authors\":\"C. Yang, D. Edelstein, L. Clevenger, A. Cowley, J. Gill, K. Chanda, A. Simon, T. Dalton, B. Agarwala, E. Cooney, D. Nguyen, T. Spooner, A. Stamper\",\"doi\":\"10.1109/IITC.2005.1499954\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper describes a new physical vapor deposition (PVD) metallization scheme that shows a better extendibility for future technology nodes as compared to the conventional scheme. In addition to reducing the thicknesses of both the diffusion barrier and the copper seed layer (Yang, C.-C. et al., MRS Adv. Metallization Conf., p.213, 2004), this new scheme also features a sacrificial process (also called barrier-first process) (Alers, G., IEEE Int. Interconnect Technology Conf., 2003), a via-punch through process (Edelstein, D. et al., IEEE Int. Reliability Physics Symp., p.316, 2004; Kuma, N. et al., MRS Adv. Metallization Conf, p.247, 2004) and a simultaneous preclean with a metal neutral deposition process (Yang et al., US Patent 6,784,105, 2004; Uzoh, C. et al., US Patents 5,930,669, 1999; 5,933,753, 1999; 6,429,519, 2002). Significant metal line and via contact resistance decrease was observed with equal or better reliability. The impact of a sputter etch integration scheme on electrical yield and reliability is also reported. The new sputter scheme decreases contact resistance at the via/interconnect interface and can offset the one resulting from dimension scaling and thus extends PVD metallization usefulness for future technologies.\",\"PeriodicalId\":156268,\"journal\":{\"name\":\"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.\",\"volume\":\"70 2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-06-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC.2005.1499954\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2005.1499954","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
摘要
本文介绍了一种新的物理气相沉积(PVD)金属化方案,与传统方案相比,该方案对未来的技术节点具有更好的可扩展性。除了减少扩散屏障和铜种子层的厚度外(Yang, c . c . c .)。等人,MRS Adv. Metallization Conf., p.213, 2004),这个新方案还具有一个牺牲过程(也称为障碍优先过程)(Alers, G., IEEE Int.)。互连技术会议,2003年),通过穿孔过程(Edelstein, D. et al., IEEE Int。可靠性物理研讨会。,第316页,2004;Kuma, N. etal ., MRS Adv. metalalization Conf, p.247, 2004)和同时预清洁与金属中性沉积工艺(Yang etal ., US Patent 6,784,105, 2004;等,美国专利5,930,669,1999;5933753年,1999年;6429519年,2002年)。观察到显著的金属线和通孔接触电阻降低,具有相同或更好的可靠性。此外,还报道了溅射蚀刻集成方案对发电效率和可靠性的影响。新的溅射方案降低了通孔/互连界面的接触电阻,可以抵消尺寸缩放造成的接触电阻,从而扩展了PVD金属化技术在未来技术中的用途。
Extendibility of PVD barrier/seed for BEOL Cu metallization
The paper describes a new physical vapor deposition (PVD) metallization scheme that shows a better extendibility for future technology nodes as compared to the conventional scheme. In addition to reducing the thicknesses of both the diffusion barrier and the copper seed layer (Yang, C.-C. et al., MRS Adv. Metallization Conf., p.213, 2004), this new scheme also features a sacrificial process (also called barrier-first process) (Alers, G., IEEE Int. Interconnect Technology Conf., 2003), a via-punch through process (Edelstein, D. et al., IEEE Int. Reliability Physics Symp., p.316, 2004; Kuma, N. et al., MRS Adv. Metallization Conf, p.247, 2004) and a simultaneous preclean with a metal neutral deposition process (Yang et al., US Patent 6,784,105, 2004; Uzoh, C. et al., US Patents 5,930,669, 1999; 5,933,753, 1999; 6,429,519, 2002). Significant metal line and via contact resistance decrease was observed with equal or better reliability. The impact of a sputter etch integration scheme on electrical yield and reliability is also reported. The new sputter scheme decreases contact resistance at the via/interconnect interface and can offset the one resulting from dimension scaling and thus extends PVD metallization usefulness for future technologies.