P. Haumesser, M. Cordeau, S. Maitrejean, T. Mourier, L. Gosset, W. Besling, G. Passemard, J. Torres
{"title":"Copper metallization for advanced interconnects: the electrochemical revolution","authors":"P. Haumesser, M. Cordeau, S. Maitrejean, T. Mourier, L. Gosset, W. Besling, G. Passemard, J. Torres","doi":"10.1109/IITC.2004.1345663","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345663","url":null,"abstract":"As ultra-large scale integration progresses, efficient copper metallization of the narrow geometries becomes challenging. In this article, the various critical steps of the damascene metallization scheme are identified. Barrier deposition, copper seeding, electroplating and copper lines capping are discussed. For each step, current approaches and related limitations are presented. The main purpose of this contribution is to show that electrochemical wet processes can be efficiently used to address the challenges raised by feature size diminution. Copper electroplating is since long used to fill trenches and vias with metal. Developments in copper electrodeposition such as medium acid chemistries or planarizing copper plating (ECMD) are described. Heterogeneous electrochemical reactions are also used in new barrier deposition techniques alternative to physical vapour deposition (PVD); the atomic layer deposition (ALD) method is one of the most promising. Electroless deposition of self aligned capping layers above copper lines is discussed as well. At last, it is shown that wet electrochemical processes can also be applied to copper seeding with seed repair techniques or by the mean or very promising electro-grafting processes, which can be used to perform efficient and robust direct to barrier plating.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123462611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Z. Gabric, W. Pamler, G. Schindler, W. Steinhogl, M. Traving
{"title":"Air gap technology by selective ozone/TEOS deposition","authors":"Z. Gabric, W. Pamler, G. Schindler, W. Steinhogl, M. Traving","doi":"10.1109/IITC.2004.1345723","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345723","url":null,"abstract":"A technology for fabrication of air gaps is presented which is based upon selective ozone/TEOS deposition of oxide. Due to the isotropic growth direction of this process, some disadvantages of the more common approaches by nonconformal CVD processes can be avoided. It is demonstrated that air gap technology has the potential to reduce the capacitance between adjacent metal lines roughly by a factor of 2 compared to full structures without air gaps.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123818011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Noguchi, K. Sato, N. Konishi, S. Uno, T. Oshima, U. Tanaka, K. Ishikawa, H. Ashihara, T. Saito, M. Kubo, H. Aoki, T. Fujiwara
{"title":"Reliability of air-gap Cu interconnect and approach to selective W sealing using 90nm node technology","authors":"J. Noguchi, K. Sato, N. Konishi, S. Uno, T. Oshima, U. Tanaka, K. Ishikawa, H. Ashihara, T. Saito, M. Kubo, H. Aoki, T. Fujiwara","doi":"10.1109/IITC.2004.1345693","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345693","url":null,"abstract":"4 levels of Cu/air-gap interconnects were successfully fabricated and the reliability of the air-gap interconnects using ArF/90nm node technology was investigated. There are distinguished improvements of leakage current and TDDB characteristics by the application of air-gap interconnects. In addition, an air-gap interconnect is improved with a selective W sealing process . This results in drastic reduction of capacitance and effective dielectric constant.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127462873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Bruynseraede, A. Fischer, F. Ungar, J. Schumacher, V. Sutcliffe, J. Michelon, K. Maex
{"title":"Comprehensive electromigration studies on dual-damascene Cu interconnects with ALD WC/sub x/N/sub y/ barriers","authors":"C. Bruynseraede, A. Fischer, F. Ungar, J. Schumacher, V. Sutcliffe, J. Michelon, K. Maex","doi":"10.1109/IITC.2004.1345666","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345666","url":null,"abstract":"Am important improvement in electromigration (EM) resistance was revealed upon the introduction of atomic-layer-deposited WCN barriers in dual-damascene Cu interconnects. At stress level EM failure were found to increase with WCN thickness and to be consistently superior compared to I-PVD deposited barriers. Although the voiding scenario is identical for both ALD and I-PVD barriers, a reduction of the current density exponent and the activation energy is observed for ALD. In contrast to the influence of WCN barrier thickness on the EM behaviour, the effect of specific pre-clean procedures prior to the ALD process turned out to the less pronounced.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127920733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Jan, N. Anand, C. Allen, J. Bielefeld, M. Buehler, V. Chikamane, K. Fischer, K. Jain, J. Jeong, S. Klopcic, T. Marieb, B. Miner, P. Nguyen, A. Schmitz, M. Nashner, T. Scherban, B. Schroeder, C. Ward, R. Wu, K. Zawadzki, S. Thompson, M. Bohr
{"title":"A 90nm high volume manufacturing logic technology featuring Cu metallization and CDO low-k ILD interconnects on 300 mm wafers","authors":"C. Jan, N. Anand, C. Allen, J. Bielefeld, M. Buehler, V. Chikamane, K. Fischer, K. Jain, J. Jeong, S. Klopcic, T. Marieb, B. Miner, P. Nguyen, A. Schmitz, M. Nashner, T. Scherban, B. Schroeder, C. Ward, R. Wu, K. Zawadzki, S. Thompson, M. Bohr","doi":"10.1109/IITC.2004.1345747","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345747","url":null,"abstract":"A leading edge 90 nm, 300 mm wafer size interconnect technology featuring Cu, CDO low-k ILD and industry's most aggressive 220 nm minimum metal pitch is being ramped into production for high performance Pentium/spl reg/ microprocessors, the first in industry, to our knowledge. Key enabling features for yield and reliability improvement to resolve challenges from weak thermo-mechanical properties of low k ILD and tight metal pitches for a production worthy interconnect process are presented.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129411880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Inductance enhancement in global clock distribution networks","authors":"H. Luman, J. Davis","doi":"10.1109/IITC.2004.1345711","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345711","url":null,"abstract":"Current research in high-speed clock distribution network focuses on techniques that require a substantial number of analog circuits such as RF clock and PLL arrays (Gutnik and Chandrakasan, 2000) or the introduction of opto-electronic devices (Mule, et al., 2002). This paper presents an alternate approach to increase the bandwidth of global clock lines by inserting passive spiral inductors in global clock networks. Simulations indicate that spiral inductor insertion can be used to obtain a five-fold increase in bandwidth. This technique can be used to extend the use of electrical clock networks currently employed in Cu-CMOS processes.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114403102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Kunimi, J. Kawahara, A. Nakano, K. Kinoshita, Y. Hayashi, M. Komatsu, Y. Seino, R. Ichikawa, Y. Takasu, T. Kikkawa
{"title":"Effect of bridging groups of precursors on modulus improvement in plasma co-polymerized low-k films","authors":"N. Kunimi, J. Kawahara, A. Nakano, K. Kinoshita, Y. Hayashi, M. Komatsu, Y. Seino, R. Ichikawa, Y. Takasu, T. Kikkawa","doi":"10.1109/IITC.2004.1345719","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345719","url":null,"abstract":"We have demonstrated that the mechanical strength of organic silica low-k films can be enhanced by introducing a reinforcement monomer in a matrix monomer under plasma excitation. The modulus improvement mechanism was investigated by analyzing the film structure. Pyrolysis gas chromatography / mass spectrometry (Py-GC/MS) revealed incorporation of a reinforcement monomer in the matrix through co-polymerization reactions. Compositional analysis of the films showed that the extent of reinforcement is associated with co-polymerization ratio or the monomer content in the film. It is also indicated that the modulus enhancement depends on the content of 3D aromatic bridge structure, which is affected by the chemical structure of the reinforcement monomers.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124486695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Yoo, S. Kondo, S. Tokitoh, A. Namiki, K. Misawa, K. Inukai, N. Ohashi, N. Kobayashi
{"title":"Characterization of patterned low-k film delamination during CMP for the 32nm node Cu/ultra low-k (k=1.6-1.8) integration","authors":"B. Yoo, S. Kondo, S. Tokitoh, A. Namiki, K. Misawa, K. Inukai, N. Ohashi, N. Kobayashi","doi":"10.1109/IITC.2004.1345761","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345761","url":null,"abstract":"Pattern dependence of ultra low-k (ULK, k=1.6-1.8) film delamination during Cu-CMP has been investigated to integrate the 32 nm node Cu/ULK damascene interconnects. A CMP mask that has various kinds of dummy-patterns was developed for quantitative characterization of the ULK film delamination. As a result, the perimeter of the pattern, which is the length along the boundary between Cu and low-k film, was found to be a determinative parameter in delamination of the patterned low-k film rather than pattern density. This is because Cu interconnects with higher-density perimeter increase the tolerance to shear stress generated by the CMP, and thus prevent the delamination due to the low mechanical strength of the ULK film (modulus; E<2GPa). A soft pad polishing was also effective in suppressing the mechanical damage. On the basis of these results, Cu damascene interconnects with ULK film were successfully integrated on 300mm wafers.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129170020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Robust multilevel interconnects with a nano-clustering porous low-k (k<2.3)","authors":"T. Nakamura, A. Nakashima","doi":"10.1109/IITC.2004.1345733","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345733","url":null,"abstract":"For 65 nm node devices and beyond, we developed a high performance porous SOD materials, nano-clustering silica (NCS). Our original nano-clustering technique can control pore sizes to less than 2.8nm and achieve a homogenous pore distribution without the use of any template materials. NCS films combine a very low dielectric constant (k<2.3) with high mechanical strength; the elastic modulus is 10 GPa and the hardness is greater than 1.0 GPa. We have successfully fabricated 200nm-pitch hybrid-ULK/Cu interconnects by application of NCS to trench layers and SiOC to via layers. The structures exhibit satisfactory electrical characteristics, reliability and framework strength for the severe requirements of 65nm node devices. 10-level interconnects using NCS for the intermediate layers were fabricated without any delamination or cracking. The results of thermal-cycle (TC) and pressure temperature humidity stress (PTHS) tests also showed the high practical reliabilities. The NCS/copper multilevel interconnects meet the 65nm-node requirements for BEOL.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114209035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Jeannot, N. Schnell, Régis Orobtchouk, J. Fédéli, F. Fusalba, Vincent Jousseaume, P. Maury, F. Gaillard, T. Benyattou, G. Passemard
{"title":"Intrachip optical interconnect: an above IC approach","authors":"S. Jeannot, N. Schnell, Régis Orobtchouk, J. Fédéli, F. Fusalba, Vincent Jousseaume, P. Maury, F. Gaillard, T. Benyattou, G. Passemard","doi":"10.1109/IITC.2004.1345766","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345766","url":null,"abstract":"This paper describes a new approach for optical interconnects, based on an above IC clock signal distribution with high compacity, using polymers with high refractive index difference. We investigate the design and its feasibility study and show the results on the first components obtained with similar materials. We demonstrate a high level of integration using materials compatible with microelectronic process, allowing an intra-chip optical distribution.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122851535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}