A 90nm high volume manufacturing logic technology featuring Cu metallization and CDO low-k ILD interconnects on 300 mm wafers

Abstract

A leading edge 90 nm, 300 mm wafer size interconnect technology featuring Cu, CDO low-k ILD and industry's most aggressive 220 nm minimum metal pitch is being ramped into production for high performance Pentium/spl reg/ microprocessors, the first in industry, to our knowledge. Key enabling features for yield and reliability improvement to resolve challenges from weak thermo-mechanical properties of low k ILD and tight metal pitches for a production worthy interconnect process are presented.