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2014 19th IEEE European Test Symposium (ETS)最新文献

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Factoring variability in the Design/Technology Co Optimisation (DTCO) in advanced CMOS 在先进CMOS的设计/技术Co优化(DTCO)中考虑可变性
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847791
A. Asenov
{"title":"Factoring variability in the Design/Technology Co Optimisation (DTCO) in advanced CMOS","authors":"A. Asenov","doi":"10.1109/ETS.2014.6847791","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847791","url":null,"abstract":"Summary form only given. This paper describes the fully automated GSS tool flow, which bridges the gap between Technology Computer Aided Design (TCAD) at the transistor level, and circuit simulations and verification. The purpose of the tool flow is twofold: (i) to allow rapid simulation-based Design-Technology Co-Optimisation (DTCO) and (ii) to allow generation of accurate compact models for Preliminary Design Kit (PDK) development at the early stages of new technology development. The aim is to capture accurately process, statistical and time dependent variability in the DTCO and early PDKs. The operation of the automated tool flow is exemplified in the comprehensive PDK compact model development for a 14 nm SOI FinFET process, and the corresponding transistor / SRAM cell co-optimisation.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134146314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
iBoX — Jitter based Power Supply Noise sensor iBoX -基于抖动的电源噪声传感器
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847830
M. Valka, A. Bosio, L. Dilillo, A. Todri, A. Virazel, P. Girard, P. Debaud, Stephane Guilhot
{"title":"iBoX — Jitter based Power Supply Noise sensor","authors":"M. Valka, A. Bosio, L. Dilillo, A. Todri, A. Virazel, P. Girard, P. Debaud, Stephane Guilhot","doi":"10.1109/ETS.2014.6847830","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847830","url":null,"abstract":"In this paper we propose a novel Power Supply Noise (PSN) sensor. It is based on timing uncertainty measure. Compared to state of the art it allows to measure the PSN events in more accurate way. The proposed sensor is actually under validation and patent reviewing process.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130802658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Property-checking based LBIST for improved diagnosability 基于属性检查的LBIST，可提高可诊断性
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847828
S. Prabhu, Vineeth V. Acharya, S. Bagri, M. Hsiao
{"title":"Property-checking based LBIST for improved diagnosability","authors":"S. Prabhu, Vineeth V. Acharya, S. Bagri, M. Hsiao","doi":"10.1109/ETS.2014.6847828","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847828","url":null,"abstract":"We propose a new property-checking-based LBIST architecture which uses hardware monitors to check certain properties in the output responses. If any property is violated, the failing property number is stored for diagnosis. The proposed architecture improves diagnosability considerably with minimal hardware overhead. Experimental results show that the diagnostic resolution achieved by our architecture is comparable to that achieved in a non-BIST setup for many circuits.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115249187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Post-bond test of Through-Silicon Vias with open defects 带开放缺陷的硅通孔粘接后测试
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847816
R. Rodríguez-Montañés, D. Arumí, J. Figueras
{"title":"Post-bond test of Through-Silicon Vias with open defects","authors":"R. Rodríguez-Montañés, D. Arumí, J. Figueras","doi":"10.1109/ETS.2014.6847816","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847816","url":null,"abstract":"Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and are susceptible to undergo defects at different stages: during their own fabrication, the bonding stage or during their life time. Typical defects are microvoids, underfilling, misalignement, pinholes in the oxide or misalignments during bonding in such a way that resistive opens become a frequent failure mechanism affecting TSVs. Although there is considerable research effort dedicated to improve TSVs testing, no much attention has been paid to weak defects, especially to weak open defects (resistive opens) causing small delays. In this work, a testing strategy is proposed to detect small delay defects by means of a post-bond oscillation test. Variations in the Duty Cycle of transmitted signals after unbalanced logic gates are shown to detect weak open defects in TSVs. HSPICE simulations including process parameter variations show the effectiveness of the method in the detection of weak open defects above 1 kΩ.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116395615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Error detection and recovery in better-than-worst-case timing designs 优于最坏情况的定时设计中的错误检测和恢复
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847811
A. Singh
{"title":"Error detection and recovery in better-than-worst-case timing designs","authors":"A. Singh","doi":"10.1109/ETS.2014.6847811","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847811","url":null,"abstract":"Better-than-worst-case timing design methodologies aim at increasing throughput by speeding up the clock to the point where circuit timing margins are reduced to zero and even beyond. In low power designs such as Razor, this efficiency improvement is translated into power savings at a fixed operational clock rate through adaptive and dynamic voltage scaling. The main challenge in such designs is the development of efficient mechanisms to detect and recover from the occasional timing errors that can occur. We survey recently published designs in this domain with a special focus on the error detection and recovery approaches employed. Experimental prototype processors implemented by ARM and Intel are also discussed.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122864007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Smart-hopping: Highly efficient ISA-level fault injection on real hardware Smart-hopping:在真实硬件上高效的isa级故障注入
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847803
Horst Schirmeier, Lars Rademacher, O. Spinczyk
{"title":"Smart-hopping: Highly efficient ISA-level fault injection on real hardware","authors":"Horst Schirmeier, Lars Rademacher, O. Spinczyk","doi":"10.1109/ETS.2014.6847803","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847803","url":null,"abstract":"Fault-injection experiments on the instruction-set architecture level are commonly used to analyze embedded software's susceptibility to hardware faults, typically involving a vast number of experiments with systematically varying fault locations and times. Determinism and high performance are the predominant requirements on fault-injection platforms. Injecting faults into a real embedded hardware platform instead of a simulator is favorable for both workload execution speed and result accuracy. The most performance-critical part of such a fault-injection platform is the “fast forward” operation, which executes the target machine code without faults until the exact dynamic instruction is reached at which the execution must be stopped to inject the next fault. Unfortunately, most embedded CPUs do not support this operation efficiently. In this paper we present an approach that speeds up fast-forwarding significantly for most workloads with minimal requirements on hardware support. Based on a previously recorded instruction trace - which is needed for systematic fault-injection experiment planning anyways - we use standard debugging hardware to advance to a chosen point in program execution with a minimal number of steps. We evaluate our FAIL* tool platform with two MiBench benchmark categories, and improve experiment throughput by up to several magnitudes compared to similar fault-injection tools in the field.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127402208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Quantitative evaluation of register vulnerabilities in RTL control paths RTL控制路径中寄存器漏洞的定量评估
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847837
Liang Chen, Mojtaba Ebrahimi, M. Tahoori
{"title":"Quantitative evaluation of register vulnerabilities in RTL control paths","authors":"Liang Chen, Mojtaba Ebrahimi, M. Tahoori","doi":"10.1109/ETS.2014.6847837","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847837","url":null,"abstract":"Radiation-induced soft error is a significant reliability issue in nanoscale technology nodes. In this paper, a novel approach based on probabilistic model checking is proposed to quantify the soft error vulnerabilities of the registers in the control paths at the Register-Transfer Level (RTL). Efficient abstraction and model simplification techniques are proposed to significantly improve the scalability of our method. The experimental results show the effectiveness of proposed techniques to successfully quantify the register vulnerabilities in the RTL design, to be used for cost-effective selective register protection.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125749697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Major eras of Design for Test 为测试设计的主要时代
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847790
W. Rhines
{"title":"Major eras of Design for Test","authors":"W. Rhines","doi":"10.1109/ETS.2014.6847790","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847790","url":null,"abstract":"From writing functional tests to managing design groups to managing major businesses, Dr. Rhines has been personally involved in the evolution of Design for Test. From this perspective, he will describe the driving forces and technologies that changed the way we design products to make them testable, and what will drive change in the future.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134490755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Logic simulation and fault collapsing with shared structurally synthesized bdds 基于共享结构合成bdd的逻辑仿真与故障崩溃
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847825
Dmitri Mironov, R. Ubar, J. Raik
{"title":"Logic simulation and fault collapsing with shared structurally synthesized bdds","authors":"Dmitri Mironov, R. Ubar, J. Raik","doi":"10.1109/ETS.2014.6847825","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847825","url":null,"abstract":"A new method for logic simulation and fault modeling in combinational circuits with Structurally Synthesized BDDs (SSBDD) is proposed. The new model is constructed by merging different super-graphs (SSBDDs) related to different circuit outputs, which share as much as possible different subgraphs (SSBDDs) representing the circuit. We call this model as Shared SSBDDs (S3BDD) where each node represents a particular signal path (or segment) of the circuit, and as well the representatives of different fault classes related to this path. A lower bound for the size of the S3BDD model for a given circuit, a method for synthesis of S3BDDs with the size close to the lower bound, and a fast logic simulation method based on S3BDDs were developed. Experimental research results support the claims about the efficiency of the model.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122235777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Shadow-scan design with low latency overhead and in-situ slack-time monitoring 具有低延迟开销和现场松弛时间监测功能的影子扫描设计
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847801
S. Sarrazin, S. Evain, I. Panades, A. Valentian, Suresh Pajaniradja, L. Naviner, V. Gherman
{"title":"Shadow-scan design with low latency overhead and in-situ slack-time monitoring","authors":"S. Sarrazin, S. Evain, I. Panades, A. Valentian, Suresh Pajaniradja, L. Naviner, V. Gherman","doi":"10.1109/ETS.2014.6847801","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847801","url":null,"abstract":"Shadow-scan solutions are proposed in order to facilitate the implementation of faster scan flip-flops (FFs) with optional support for in-situ slack-time monitoring. These solutions can be applied to system FFs placed at the end of timing-critical paths while standard-scan cells are deployed in the rest of the system. Automated scan stitching and automated test pattern generation (ATPG) can be performed transparently with commercial tools. The generated test patterns cover not only the mission logic but also the monitoring infrastructure. The latency of itc'99 benchmark circuits could be reduced with up to 10% while the stuck-at fault coverage (FC) was preserved as compared to circuit versions with full standard-scan design. Limited variations in the number of test patterns were observed when support for in-situ slack-time monitoring was provided.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128149950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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