Error detection and recovery in better-than-worst-case timing designs

Abstract

Better-than-worst-case timing design methodologies aim at increasing throughput by speeding up the clock to the point where circuit timing margins are reduced to zero and even beyond. In low power designs such as Razor, this efficiency improvement is translated into power savings at a fixed operational clock rate through adaptive and dynamic voltage scaling. The main challenge in such designs is the development of efficient mechanisms to detect and recover from the occasional timing errors that can occur. We survey recently published designs in this domain with a special focus on the error detection and recovery approaches employed. Experimental prototype processors implemented by ARM and Intel are also discussed.