Logic simulation and fault collapsing with shared structurally synthesized bdds

A new method for logic simulation and fault modeling in combinational circuits with Structurally Synthesized BDDs (SSBDD) is proposed. The new model is constructed by merging different super-graphs (SSBDDs) related to different circuit outputs, which share as much as possible different subgraphs (SSBDDs) representing the circuit. We call this model as Shared SSBDDs (S3BDD) where each node represents a particular signal path (or segment) of the circuit, and as well the representatives of different fault classes related to this path. A lower bound for the size of the S3BDD model for a given circuit, a method for synthesis of S3BDDs with the size close to the lower bound, and a fast logic simulation method based on S3BDDs were developed. Experimental research results support the claims about the efficiency of the model.