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2014 19th IEEE European Test Symposium (ETS)最新文献

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Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs 老化和电压标度对sram fpga中子诱导软误差率的影响
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847845
F. Kastensmidt, Jorge Tonfat, T. H. Both, P. Rech, G. Wirth, R. Reis, Florent Bruguier, P. Benoit, L. Torres, C. Frost
{"title":"Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs","authors":"F. Kastensmidt, Jorge Tonfat, T. H. Both, P. Rech, G. Wirth, R. Reis, Florent Bruguier, P. Benoit, L. Torres, C. Frost","doi":"10.1109/ETS.2014.6847845","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847845","url":null,"abstract":"This work investigates the effects of aging and voltage scaling in neutron-induced bit-flip in SRAM-based FPGAs. Experimental results show that aging and voltage scaling can increase in at least two times the susceptibility of SRAM-based FPGAs to Soft Error Rate (SER). These results are innovative, because they combine three real effects that occur in programmable circuits operating at ground-level applications. In addition, a model at electrical simulation for aging, soft error and different voltages was described to investigate the effects observed at the practical neutron irradiation experiment. Results can guide designers to predict soft error effects during the lifetime of devices operating in different power supply mode.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121303845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Interleaved scrambling technique: A novel low-power security layer for cache memories 交错置乱技术:一种新型的低功耗高速缓存存储器安全层
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847844
M. Neagu, L. Miclea, S. Manich
{"title":"Interleaved scrambling technique: A novel low-power security layer for cache memories","authors":"M. Neagu, L. Miclea, S. Manich","doi":"10.1109/ETS.2014.6847844","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847844","url":null,"abstract":"Memory systems security has increased over the last decade due to the sensitive information which is stored in plain text. Device specific attacks, such as cold-boot and side-channel monitoring have been reported as being successfully in retrieving encryption and private keys from algorithms like AES and RSA. In this paper, we propose a new technique of securing the cache memories by scrambling the stored data that uses interleaved scrambling vectors which reduce the power consumption if compared to the standard scrambling technique. Dissemination rules for the retained data in the cache are employed, in order to make data unusable if retrieved successfully by any type of attack. The proposed technique is analyzed and evaluated from several points of views, including area overhead, power consumption and time performance.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122422633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Site dependencies in a multisite testing environment 多站点测试环境中的站点依赖关系
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847808
T. Lehner, Andreas Kuhr, M. Wahl, R. Brück
{"title":"Site dependencies in a multisite testing environment","authors":"T. Lehner, Andreas Kuhr, M. Wahl, R. Brück","doi":"10.1109/ETS.2014.6847808","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847808","url":null,"abstract":"This paper describes a statistical approach for online yield analysis for multisite testing of highly reliable automotive ICs as well as the implementation of the system for testing mostly analog circuits. The core of the approach is the yield analysis of the different sites based on statistical measures. The system has been implemented as part of the production environment of Elmos Semiconductor. It is in daily use. Although the analysis tool has been accepted reluctantly, it soon became an excellent tool with a significant impact on test quality and cost saving.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115425065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Automatic correction of certain design errors using mutation technique 利用突变技术自动修正某些设计错误
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847833
Payman Behnam, B. Alizadeh, Z. Navabi
{"title":"Automatic correction of certain design errors using mutation technique","authors":"Payman Behnam, B. Alizadeh, Z. Navabi","doi":"10.1109/ETS.2014.6847833","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847833","url":null,"abstract":"In this paper, we introduce a new technique that makes use of satisfiability (SAT) based debugging techniques along with a mutation-based technique to correct certain design errors in digital designs automatically. The experimental results demonstrate that our proposed method enables us to locate and correct multiple bugs by targeting gate replacements and wire exchanging within reasonable run-time and memory usage for several designs.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130838917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Using dynamic shift to reduce test data volume in high-compression designs 在高压缩设计中使用动态移位来减少测试数据量
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847822
X. Lin, M. Kassab, J. Rajski
{"title":"Using dynamic shift to reduce test data volume in high-compression designs","authors":"X. Lin, M. Kassab, J. Rajski","doi":"10.1109/ETS.2014.6847822","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847822","url":null,"abstract":"This paper presents a test data volume (TDV) reduction method for designs utilizing extremely high compression configurations, and it enables reducing the pin count interfacing with the Automatic Test Equipment. Based on the encoding requirements for every test cube, the proposed test compression method changes the number of shift cycles used to load the test stimuli dynamically. No additional pins or modification of the existing scan chains is needed, making the proposed method work seamlessly with existing sequential linear decompressors. Experimental results obtained for industrial designs demonstrate the effectiveness of the proposed method at reducing TDV in high compression configurations.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130892641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Output-bit selection with X-avoidance using multiple counters for test-response compaction 输出位选择与x避免使用多个计数器测试响应压缩
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847823
Wei-Cheng Lien, Kuen-Jong Lee, K. Chakrabarty, Tong-Yu Hsieh
{"title":"Output-bit selection with X-avoidance using multiple counters for test-response compaction","authors":"Wei-Cheng Lien, Kuen-Jong Lee, K. Chakrabarty, Tong-Yu Hsieh","doi":"10.1109/ETS.2014.6847823","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847823","url":null,"abstract":"Output-bit selection is a recently proposed test-response compaction approach that can effectively deal with aliasing, unknown-value, and low-diagnosis problems. This approach has been implemented using a single counter and a multiplexer without considering unknown values. Also, such an implementation may require the application of a pattern multiple times in order to observe all selected responses. In this paper, we present a multiple-counter-based architecture with a new selection algorithm that can avoid most unknown-values yet achieve high compaction ratio. The remaining small number of unknowns can then be dealt with using some simple masking logic. Experiments on IWLS'05 circuits show that even with 16% unknown responses, all unknown values can be handled with 88.92%~93.21% response-volume reduction still achieved and only a moderate increase in test-application time.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124806460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Incremental computation of delay fault detection probability for variation-aware test generation 变化感知测试生成中的延迟故障检测概率增量计算
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847805
Marcus Wagner, H. Wunderlich
{"title":"Incremental computation of delay fault detection probability for variation-aware test generation","authors":"Marcus Wagner, H. Wunderlich","doi":"10.1109/ETS.2014.6847805","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847805","url":null,"abstract":"Large process variations in recent technology nodes present a major challenge for the timing analysis of digital integrated circuits. The optimization decisions of a statistical delay test generation method must therefore rely on the probability of detecting a target delay fault with the currently chosen test vector pairs. However, the huge number of probability evaluations in practical applications creates a large computational overhead. To address this issue, this paper presents the first incremental delay fault detection probability computation algorithm in the literature, which is suitable for the inner loop of automatic test pattern generation methods. Compared to Monte Carlo simulations of NXP benchmark circuits, the new method consistently shows a very large speedup and only a small approximation error.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129798499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Systematic generation of diagnostic software-based self-test routines for processor components 基于诊断软件的处理器组件自检程序的系统生成
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847795
Mario Schölzel, T. Koal, H. Vierhaus
{"title":"Systematic generation of diagnostic software-based self-test routines for processor components","authors":"Mario Schölzel, T. Koal, H. Vierhaus","doi":"10.1109/ETS.2014.6847795","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847795","url":null,"abstract":"Recently some fine-grained self-repair techniques for processors have been published that can handle permanent faults in particular components of a processor in-the-field. Unfortunately, the generation of diagnostic tests that can be used in-the-field for fault localization in these components is not solved satisfactorily. A few papers paid attention on improving the diagnostic capabilities of software-based self-test programs, but with emphasis on manufacturing test. This paper presents a systematic approach for the generation of test programs for diagnostic tests in-the-field. Moreover, the test program is generated in such a way that it specifically targets for faults that can be handled with an available self-repair method. The functional test programs are constructed from test patterns that can be generated with standard ATPG tools. The results show that diagnostic test programs will have an overhead in test program length ranging from 0% to 391% compared with non-diagnostic test programs.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128787935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Cell-aware experiences in a high-quality automotive test suite 高质量汽车测试套件中的细胞感知体验
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847814
F. Hapke, R. Arnold, Matthias Beck, M. Baby, S. Straehle, J. Gonçalves, A. Panait, R. Behr, Gwenolé Maugard, A. Prashanthi, J. Schlöffel, W. Redemund, Andreas Glowatz, A. Fast, J. Rajski
{"title":"Cell-aware experiences in a high-quality automotive test suite","authors":"F. Hapke, R. Arnold, Matthias Beck, M. Baby, S. Straehle, J. Gonçalves, A. Panait, R. Behr, Gwenolé Maugard, A. Prashanthi, J. Schlöffel, W. Redemund, Andreas Glowatz, A. Fast, J. Rajski","doi":"10.1109/ETS.2014.6847814","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847814","url":null,"abstract":"High quality is an absolute necessity for automotive designs. This paper describes an approach to improve the overall defect coverage for CMOS-based high quality automotive designs. We present results from a cell-aware (CA) characterization flow for 216 cells, the pattern generation flow for a 130nm smart power design, and high-volume production test results achieved after testing multimillion parts. The idea behind CA tests is to detect cell-internal (CI) bridges, opens, leaking and high resistive transistor defects which are undetected with state-of-the-art tests. The production test results have shown that the CA tests detect various failing parts during a first wafer sort test which still resulted into unique failing parts after a second wafer sort test done at a different temperature and with additional tests. The obtained results encouraged us to continue this work beyond this paper to run further experiments with the final goal to eliminate the stuck-at (SA) and transition delay (TR) test by simultaneously improving the quality with CA tests which are a superset of SA and TR tests.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"12 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120997825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A true random number generator with on-line testability 具有在线可测试性的真随机数生成器
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847799
E. Böhl, Matthew Lewis, S. Galkin
{"title":"A true random number generator with on-line testability","authors":"E. Böhl, Matthew Lewis, S. Galkin","doi":"10.1109/ETS.2014.6847799","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847799","url":null,"abstract":"True random number generators (TRNGs) are widely used throughout cryptography. They are used in the challenge response authentication procedures, key generation and for hardening measures against power analysis attacks. An important feature of each TRNG is true randomness. Such randomness can be obtained from random physical effects like noise. In order to make a TRNG usable for different semiconductor technologies (including FPGAs) only digital standard library cells can be used. One possible type of TRNG that can be realized with only standard library cells is based on ring os-cillators. Such a TRNG was implemented in a test chip and investigated in combination with a simple post processing. Different on-line testability measures of the TRNG are proposed. The solution is compared with other ones.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127377486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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