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2014 19th IEEE European Test Symposium (ETS)最新文献

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On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs 2.5 d ic中高速中间线的动态时间感知内置自修复
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847841
Shi-Yu Huang, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng
{"title":"On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs","authors":"Shi-Yu Huang, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng","doi":"10.1109/ETS.2014.6847841","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847841","url":null,"abstract":"Interposer is a critical component in a 2.5-D IC as it serves as a common platform upon which multiple known good dies are bonded. Any defect in an interposer will lead to a loss of compound yield. To avoid such a last-minute yield loss, we propose a timing-aware Built-In Self-Repair method to increase the fault tolerance of high-speed interposer wires. The most unique feature of our method as compared to previous works is that ours can repair not only catastrophic faults, but also timing faults. We present an on-the-fly test-and-repair flow that can seamlessly link Pulse-Vanishing Test, a previous timing-aware interconnect test method, with a popular redundancy structure.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115829287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Sat-based speedpath debugging using waveforms 基于卫星的高速通道调试使用波形
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847802
M. Dehbashi, G. Fey
{"title":"Sat-based speedpath debugging using waveforms","authors":"M. Dehbashi, G. Fey","doi":"10.1109/ETS.2014.6847802","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847802","url":null,"abstract":"A major concern in the design of high performance VLSI circuits is speedpath debugging. This is due to the fact that timing variations induced by process variations and environmental effects are increasing as the size of VLSI circuits is shrinking. In this paper, a speedpath debugging approach based on Boolean Satisfiability (SAT) is proposed. The approach takes waveforms of the signals of a circuit into account. Waveforms and their propagation are encoded using SAT. Also, timing variation models for slowdown and speedup of each gate are incorporated into the model. The whole timing variation is controlled by a unit called variation control. Having an Erroneous Trace (ET) due to timing variation, our debug engine automatically finds potential failing speedpaths. The experimental results on ISCAS benchmarks show efficiency and diagnosis accuracy of our approach. The approach can also localize potential failing speedpaths for the multiplier circuit c6288 that has a large number of paths.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131396353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Design of low cost fault tolerant analog circuits using real-time learned error compensation 基于实时学习误差补偿的低成本容错模拟电路设计
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847838
Suvadeep Banerjee, Álvaro Gómez-Pau, A. Chatterjee
{"title":"Design of low cost fault tolerant analog circuits using real-time learned error compensation","authors":"Suvadeep Banerjee, Álvaro Gómez-Pau, A. Chatterjee","doi":"10.1109/ETS.2014.6847838","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847838","url":null,"abstract":"Analog checksum based fault tolerance for linear circuits has been proposed in the past but remains a theoretical artifact due to the high cost and complexity of error compensation while other redundancy based methods have prohibitive overheads. To resolve this, new low cost error compensation methods for widely used linear analog circuits are developed in this research. Trial and error based compensation learning methods combined with the use of less than minimum distance codes are used for failure tolerance. This results in significant hardware savings over prior correction schemes with minimal increase in error correction latency. It is shown how dual failures in analog circuits, not possible with existing techniques, can be compensated using the proposed fault-learning approach.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125326424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A novel adaptive fault tolerant flip-flop architecture based on TMR 一种基于TMR的自适应容错触发器结构
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847831
Luca Cassano, A. Bosio, G. D. Natale
{"title":"A novel adaptive fault tolerant flip-flop architecture based on TMR","authors":"Luca Cassano, A. Bosio, G. D. Natale","doi":"10.1109/ETS.2014.6847831","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847831","url":null,"abstract":"The use of Triple Modular Redundancy (TMR) was historically introduced long time ago for improving reliability of computer systems [1]. Recently, the advances in miniaturizing of CMOS devices made digital circuits more and more unreliable. The current trend goes towards the Internet of Things and the cloud computing, where small devices have high requirements in terms of reduced power consumption and increased reliability [2]. Classical TMR solutions allow for high reliability but they cannot satisfy low-power require-ments, since they consume about three times more than the equivalent single device. However, the type of applications that are implemented in the new cloud scenario do not require high reliability all the time, but it can be assumed that some computations are more important, and thus require to be executed by a reliable hardware, while other computations are less important, and thus they can tolerate failures [3].","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126967895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Model based generation of high coverage test suites for embedded systems 基于模型的嵌入式系统高覆盖率测试套件生成
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847843
Orlando Ferrante, A. Ferrari, Marco Marazza
{"title":"Model based generation of high coverage test suites for embedded systems","authors":"Orlando Ferrante, A. Ferrari, Marco Marazza","doi":"10.1109/ETS.2014.6847843","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847843","url":null,"abstract":"In this paper an algorithm for the model-based generation of high coverage test suites for embedded systems using a combination of model checking and optimization techniques is described. The algorithm is able to compute high coverage test suites starting from a formal model of the System Under Test. The novelty of the proposed method resides in the formulation of an incremental test synthesis strategy combining bounded model checking with an optimization-based formulation of the test case generation problem.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124518064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Reconfigurable high performance architectures: How much are they ready for safety-critical applications? 可重构高性能架构:它们为安全关键型应用做好了多少准备?
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847820
D. Sabena, L. Sterpone, Mario Schölzel, T. Koal, H. Vierhaus, S. Wong, R. Glein, F. Rittner, C. Stender, Mario Porrmann, J. Hagemeyer
{"title":"Reconfigurable high performance architectures: How much are they ready for safety-critical applications?","authors":"D. Sabena, L. Sterpone, Mario Schölzel, T. Koal, H. Vierhaus, S. Wong, R. Glein, F. Rittner, C. Stender, Mario Porrmann, J. Hagemeyer","doi":"10.1109/ETS.2014.6847820","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847820","url":null,"abstract":"Reconfigurable architectures are increasingly employed in a large range of embedded applications, mainly due to their ability to provide high performance and high flexibility, combined with the possibility to be tuned according to the specific task they address. Reconfigurable systems are today used in several application areas, and are also suitable for systems employed in safety-critical environments. The actual development trend in this area is focused on the usage of the reconfigurable features to improve the fault tolerance and the self-test and the self-repair capabilities of the considered systems. The state-of-the-art of the reconfigurable systems is today represented by Very Long Instruction Word (VLIW) processors and reconfigurable systems based on partially reconfigurable SRAM-based FPGAs. In this paper, we present an overview and accurate analysis of these two type of reconfigurable systems. The content of the paper is focused on analyzing design features, fail-safe and reconfigurable features oriented to self-adaptive mitigation and redundancy approaches applied during the design phase. Experimental results reporting a clear status of the test data and fault tolerance robustness are detailed and commented.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131768572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Reducing embedded software radiation-induced failures through cache memories 通过缓存存储器减少嵌入式软件辐射引起的故障
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847793
Thiago Santini, P. Rech, G. Nazar, L. Carro, F. Wagner
{"title":"Reducing embedded software radiation-induced failures through cache memories","authors":"Thiago Santini, P. Rech, G. Nazar, L. Carro, F. Wagner","doi":"10.1109/ETS.2014.6847793","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847793","url":null,"abstract":"Cache memories are traditionally disabled in space-level and safety-critical applications, since it was believed that the sensitive area they introduce would compromise the system reliability. As technology has evolved, the speed gap between logic and main memory has increased in such a way that disabling caches slows the code much more than in the past. As a result, the processor is exposed for a much longer time in order to compute the same workload. In this paper we demonstrate that, on modern embedded processors, enabling caches may bring benefits to critical systems: the larger exposed area may be compensated by the shorter exposure time, leading to an overall improved reliability. We describe the Mean Workload Between Failures, an intuitive metric to evaluate the impact of enabling caches for a given generic application error rate. The proposed metric is experimentally validated through an extensive radiation test campaign using a 28 nm off-the-shelf ARM-based SoC as a case study. The failure probability of the bare-metal application is decreased when the L1 cache is enabled but increased when L2 is also enabled. We also discuss when L2 caches could make the device more reliable.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"471 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133407224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Optimization of analog fault coverage by exploiting defect-specific masking 利用缺陷特定掩蔽优化模拟故障覆盖
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847817
Anthony Coyette, G. Gielen, Ronny Vanhooren, Wim Dobbelaere
{"title":"Optimization of analog fault coverage by exploiting defect-specific masking","authors":"Anthony Coyette, G. Gielen, Ronny Vanhooren, Wim Dobbelaere","doi":"10.1109/ETS.2014.6847817","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847817","url":null,"abstract":"A new method is presented to detect catastrophic defects from the signal analysis of dynamic current consumption waveforms of analog circuits. While other techniques use the whole information in a Root-Mean-Square computation or in black-box techniques such as a neural network, the central point of this work resides in the selection of waveform samples to create a signature able to discriminate a defective circuit from a fault-free circuit. The selection of samples is implemented by the introduction of binary vectors to partially mask the data. Confronted with process variations, this technique offers the advantage of being straightforward and simple to implement in Automated Test Equipments. The generation of the masks is optimized to improve the defect coverage by means of a genetic algorithm maximizing the distance between the signature of the fault-free circuit and a faulty circuit. Results from simulations on industrial circuits show that the number of detected defects can be nearly doubled for specific stimuli.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126955894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A generic and high-level model of large unreliable NoCs for fault tolerance and performance analysis 大型不可靠noc的通用高级模型，用于容错和性能分析
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847827
Fabien Chaix, N. Zergainoh, M. Nicolaidis
{"title":"A generic and high-level model of large unreliable NoCs for fault tolerance and performance analysis","authors":"Fabien Chaix, N. Zergainoh, M. Nicolaidis","doi":"10.1109/ETS.2014.6847827","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847827","url":null,"abstract":"The integration of more and more computing cores into processors drives the adoption of larger and larger Network-on-Chips (NoCs). Concurrently, the decreasing reliability of 1 the latest technologies promotes the utilization of fault-tolerant techniques. Unfortunately, the understanding of fault-tolerant NoCs is increasingly difficult as interconnect scale up, because they require the combination of more and more complex and heterogeneous techniques. In this paper, an high-level model named VOCIS is presented, in order to ease the comprehension and analysis of large unreliable NoCs. This model features a 3D Graphical User Interface (GUI), that offers an effective and in-depth visualization of interconnects. A few analytical measurements provided directly by VOCIS are also presented, in order to assess quantitatively the impact of defects and corresponding fault-tolerant techniques.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122119026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An off-line MDSI interconnect BIST incorporated in BS 1149.1 脱机MDSI互连BIST纳入BS 1149.1
2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847847
Marzieh Mohammadi, Somayeh Sadeghi Kohan, N. Masoumi, Z. Navabi
{"title":"An off-line MDSI interconnect BIST incorporated in BS 1149.1","authors":"Marzieh Mohammadi, Somayeh Sadeghi Kohan, N. Masoumi, Z. Navabi","doi":"10.1109/ETS.2014.6847847","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847847","url":null,"abstract":"This paper presents an off-line interconnect test methodology that implements the MDSI (Maximal Dominant Signal Integrity) crosstalk fault model. The test methodology consists of MDSI test pattern generators and response analyzers that are incorporated into the IEEE BS 1149.1 Standard on the two sides of an interconnect. This work is the first in implementing MDSI hardware structure. Our method is compared with hardware structures implementing MA interconnect tests.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124187034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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