Sat-based speedpath debugging using waveforms

Abstract

A major concern in the design of high performance VLSI circuits is speedpath debugging. This is due to the fact that timing variations induced by process variations and environmental effects are increasing as the size of VLSI circuits is shrinking. In this paper, a speedpath debugging approach based on Boolean Satisfiability (SAT) is proposed. The approach takes waveforms of the signals of a circuit into account. Waveforms and their propagation are encoded using SAT. Also, timing variation models for slowdown and speedup of each gate are incorporated into the model. The whole timing variation is controlled by a unit called variation control. Having an Erroneous Trace (ET) due to timing variation, our debug engine automatically finds potential failing speedpaths. The experimental results on ISCAS benchmarks show efficiency and diagnosis accuracy of our approach. The approach can also localize potential failing speedpaths for the multiplier circuit c6288 that has a large number of paths.