A generic and high-level model of large unreliable NoCs for fault tolerance and performance analysis

Abstract

The integration of more and more computing cores into processors drives the adoption of larger and larger Network-on-Chips (NoCs). Concurrently, the decreasing reliability of 1 the latest technologies promotes the utilization of fault-tolerant techniques. Unfortunately, the understanding of fault-tolerant NoCs is increasingly difficult as interconnect scale up, because they require the combination of more and more complex and heterogeneous techniques. In this paper, an high-level model named VOCIS is presented, in order to ease the comprehension and analysis of large unreliable NoCs. This model features a 3D Graphical User Interface (GUI), that offers an effective and in-depth visualization of interconnects. A few analytical measurements provided directly by VOCIS are also presented, in order to assess quantitatively the impact of defects and corresponding fault-tolerant techniques.