2014 19th IEEE European Test Symposium (ETS)最新文献_第5页

A new efficiency criterion for security oriented error correcting codes 一种新的面向安全的纠错码效率准则

2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847800

Yaara Neumeier, O. Keren

引用次数: 8

A distance-based test cube merging procedure for compatible and incompatible test cubes 兼容和不兼容测试多维数据集的基于距离的测试多维数据集合并过程

2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847824

I. Pomeranz

引用次数: 0

Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation 评估设备稳健性和减轻电离辐射的故障注入和容错方法

2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847812

D. Alexandrescu, L. Sterpone, C. López-Ongil

{"title":"Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation","authors":"D. Alexandrescu, L. Sterpone, C. López-Ongil","doi":"10.1109/ETS.2014.6847812","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847812","url":null,"abstract":"Traditionally, heavy ion radiation effects affecting digital systems working in safety critical application systems has been of huge interest. Nowadays, due to the shrinking technology process, Integrated Circuits became sensitive also to other kinds of radiation particles such as neutron that can exist at the earth surface and affects ground-level safety critical applications such as automotive or medical systems. The process of analyzing and hardening digital devices against soft errors implies rising the final cost due to time expensive fault injection campaigns and radiation tests, as well as reducing system performance due to the insertion of redundancy-based mitigation solutions. The main industrial problem arising is the localization of the critical elements in the circuit in order to apply optimal mitigation techniques. The proposal of this tutorial is to present and discuss different solutions currently available for assessing and implementing the fault tolerance of digital circuits, not only when the unique design description is provided but also at the component level, especially when Commercial-of-the-shelf (COTS) devices are selected.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128409067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Towards a general purpose mixed-signal instrumentation layer in the die stack of a 3D-SIC 3D-SIC芯片堆叠中通用混合信号仪表层的研究

2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847832

Shudong Lin, G. Roberts

引用次数: 2

Improving polynomial datapath debugging with HEDs 改进用赫德调试多项式数据路径

2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847797

Somayeh Sadeghi Kohan, Payman Behnam, B. Alizadeh, M. Fujita, Z. Navabi

引用次数: 6

INL systematic reduced-test technique for Pipeline ADCs 流水线adc系统简化测试技术

2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847818

E. Peralías, A. Ginés, A. Rueda

引用次数: 10

Variation-aware deterministic ATPG 变化感知确定性ATPG

2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847806

M. Sauer, I. Polian, M. Imhof, A. Mumtaz, E. Schneider, A. Czutro, H. Wunderlich, B. Becker

引用次数: 17

Triple error detection for Imai-Kamiyanagi codes based on subsyndrome computations 基于子群计算的Imai-Kamiyanagi码三重错误检测

2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847840

Christian Badack, M. Gössel

引用次数: 0

Quantified contribution of design for manufacturing to yield at 28nm 量化设计对28nm制程产率的贡献

2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847815

T. Herrmann, S. Malik, S. Madhavan

{"title":"Quantified contribution of design for manufacturing to yield at 28nm","authors":"T. Herrmann, S. Malik, S. Madhavan","doi":"10.1109/ETS.2014.6847815","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847815","url":null,"abstract":"Yield is the single most important criterion which drives the economics of our industry, impacting the bottom line directly. It is a well understood fact that both foundries and fabless companies have an extremely strong interest in achieving high yield as quickly as possible to meet the economies of scale and rapid time to market. At the 28nm node and below, implementation of DFM is believed to be particularly critical to enable a fast yield ramp. Quantification of the yield impact of various DFM enhancements is crucial to drive the appropriate design tradeoffs. In this paper we present an analysis of yield impact of DFM features over the duration of technology and product yield ramp for the 28nm node. Yield has inherent variation due to nature of its dependency on multiple factors and stages which makes it difficult to attribute yield signal to a small action in a long chain of event, from design to fabrication, leading to successful yield. We created a set of designs in 28nm, with and without DFM, where DFM changes were done only opportunistically. After finishing these designs, both the unmodified and the DFM enhanced layouts were placed side by side on the test chip reticles. Both instances got tested over long time for yield evaluation on silicon to create enormous amount of data which we analyzed and present in this paper. For analysis of all this data, we compare different statistical methods to understand the same and present challenges faced using these methods. We conclude with successful application of Matched Pair statistical method that quantified yield sensitivity to the DFM design changes.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116128452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Optimization-based multiple target test generation for highly compacted test sets 基于优化的高度压缩测试集的多目标测试生成

2014 19th IEEE European Test Symposium (ETS) Pub Date : 2014-05-26 DOI: 10.1109/ETS.2014.6847807

Stephan Eggersglüß, K. Schmitz, Rene Krenz-Baath, R. Drechsler

引用次数: 24