21st International Conference on VLSI Design (VLSID 2008)最新文献_第4页

Watermarking Video Clips with Workload Information for DVS 水印视频剪辑与负载信息的DVS

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.103

Yicheng Huang, S. Chakraborty, Ye Wang

引用次数: 2

Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture 基于混合纳米- cmos结构的容错计算

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.71

M. O. Simsir, S. Cadambi, Franjo Ivancic, M. Rötteler, N. Jha

{"title":"Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture","authors":"M. O. Simsir, S. Cadambi, Franjo Ivancic, M. Rötteler, N. Jha","doi":"10.1109/VLSI.2008.71","DOIUrl":"https://doi.org/10.1109/VLSI.2008.71","url":null,"abstract":"Architectures based on nanoscale molecular devices are attracting attention for replacing CMOS architectures at the end of the semiconductor roadmap. The two most promising nanotechnologies, according to ITRS, are silicon nanowires and carbon nanotubes. Although they offer unmatched densities for building logic, interconnect and memory, they suffer from very defect-prone manufacturing processes. This is further exacerbated by testing complexities where it is nearly impossible to detect all defects in a large nanoscale chip. Furthermore, the small structures in nanoscale architectures are susceptible to transient faults which can produce arbitrary soft errors. As a result, fault tolerance is necessary to make nanoscale architectures practical and realistic. We propose an architecture that can tolerate a large number of undetected manufacturing faults as well as a large rate of transient faults. Our architecture is characterized by multiple levels of redundancy and majority voting to correct errors caused by such faults. A key aspect of the architecture is that it contains a judicious balance of both nanoscale and traditional CMOS components. A companion to the architecture is a compiler with heuristics tailored to quickly and compactly map logic onto partially defective components. Experimental results demonstrate the efficacy of the architecture.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133376824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Memory Architecture Exploration Framework for Cache Based Embedded SOC 基于缓存的嵌入式SOC内存架构探索框架

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.113

T. Kumar, C. Ravikumar, R. Govindarajan

{"title":"Memory Architecture Exploration Framework for Cache Based Embedded SOC","authors":"T. Kumar, C. Ravikumar, R. Govindarajan","doi":"10.1109/VLSI.2008.113","DOIUrl":"https://doi.org/10.1109/VLSI.2008.113","url":null,"abstract":"Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133146007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Compact Modeling of Suspended Gate FET 悬栅场效应管的紧凑建模

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.11

Y. Chauhan, D. Tsamados, N. Abelé, Christoph Eggimann, M. Declercq, A. Ionescu

引用次数: 12

A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits 一种抗组合电路软误差和瞬态的稳健触发器结构

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.99

Aditya Jagirdar, Roystein Oliveira, T. Chakraborty

引用次数: 4

Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors 可扩展处理器的合法自定义指令的详尽枚举

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.93

N. Pothineni, Anshul Kumar, K. Paul

{"title":"Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors","authors":"N. Pothineni, Anshul Kumar, K. Paul","doi":"10.1109/VLSI.2008.93","DOIUrl":"https://doi.org/10.1109/VLSI.2008.93","url":null,"abstract":"Today's customizable processors allow the to augment the base processor with custom accelerators. By choosing appropriate set of accelerators, designer can significantly enhance the performance and power of an application. Due to the large number of accelerator choices and their complex trade-offs among reuse, gain and area, manually deciding the optimal combination of accelerators is quite cumbersome and time consuming. This calls for CAD tools that select optimal combination of accelerators by thoroughly searching the entire design space. The term pattern is commonly used to represent the computation performed by a custom accelerator. In this paper, we propose an algorithm for rapidly enumerating all the legal patterns taking into account several constraints posed by a typical micro-architecture. The proposed algorithm achieves significant reduction in run-time by a) enumerating the patterns in the increasing order of sizes and b) relating the characteristics of a (k + 1) node pattern with the characteristics of its k node subgraphs. Also, in scenarios where I/O is not a bottleneck, designer can optionally relax the I/O constraint and our algorithm efficiently enumerates all legal I/O unbound legal patterns. The experimental evidence indicate an order of two run-time speedup over state of the art techniques.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129084832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

OpenSPARC - A Scalable Chip Multi-Threading Design 一个可扩展的芯片多线程设计

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.136

Dwayne Lee

引用次数: 4

Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design 利用变周期传输实现高效节能片上互连设计

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.15

T. V. Kalyan, M. Mutyam, V. Pasupureddi

引用次数: 6

Gateway to Chips: High Speed I/O Signalling and Interface 网关到芯片:高速I/O信号和接口

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.121

N. Kumar, S. Velu, Rajan Verma

{"title":"Gateway to Chips: High Speed I/O Signalling and Interface","authors":"N. Kumar, S. Velu, Rajan Verma","doi":"10.1109/VLSI.2008.121","DOIUrl":"https://doi.org/10.1109/VLSI.2008.121","url":null,"abstract":"The design of inputs and outputs to integrated circuits has traditionally been a straightforward task involving procurement of a specification and its implementation. In the past few technology generations design and implementation of integrated circuit I/O's have become much more complex. Just as Moore's Law predicts that functions per chip will double every 1.5-2 years to keep up with consumer demand, there is a corresponding demand for processing electrical signals at progressively higher rates. The international technology roadmap for semiconductors (ITRS) predicts the I/O bandwidth (Gb/s) for high performance ASICs to be 30 Gb/s by the year 2015. Adding to the complexity is the need to conform to a plethora of emerging I/O specifications and continued focus on reliability regarding electro static discharge (ESD) and simultaneous switching noise (SSN), and the circuit designer has about as much challenges as one can stand. This tutorial presents the techniques and methods employed to build a low power, high bandwidth, highly reliable I/O. It covers the popular signaling standards like LVDS, DDR, XAUI and PCI-Express. Also to be covered are concepts of ESD and Signal Integrity. This section of the tutorial will cover the origins of ESD failures in chips, circuit and layout guidelines to avoid ESD failures and ESD testing procedures. Finally, the tutorial will give a detailed architectural overview of various emerging I/O's such as the DDR, LVDS, and the USB-PHY.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128612551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures 在片上通信架构的系统级功率探索中纳入PVT变化

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.14

S. Pasricha, Young-Hwan Park, F. Kurdahi, N. Dutt

引用次数: 9