Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors

Abstract

Today's customizable processors allow the to augment the base processor with custom accelerators. By choosing appropriate set of accelerators, designer can significantly enhance the performance and power of an application. Due to the large number of accelerator choices and their complex trade-offs among reuse, gain and area, manually deciding the optimal combination of accelerators is quite cumbersome and time consuming. This calls for CAD tools that select optimal combination of accelerators by thoroughly searching the entire design space. The term pattern is commonly used to represent the computation performed by a custom accelerator. In this paper, we propose an algorithm for rapidly enumerating all the legal patterns taking into account several constraints posed by a typical micro-architecture. The proposed algorithm achieves significant reduction in run-time by a) enumerating the patterns in the increasing order of sizes and b) relating the characteristics of a (k + 1) node pattern with the characteristics of its k node subgraphs. Also, in scenarios where I/O is not a bottleneck, designer can optionally relax the I/O constraint and our algorithm efficiently enumerates all legal I/O unbound legal patterns. The experimental evidence indicate an order of two run-time speedup over state of the art techniques.