基于缓存的嵌入式SOC内存架构探索框架

T. Kumar, C. Ravikumar, R. Govindarajan
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引用次数: 12

摘要

当今功能丰富的多媒体产品需要具有复杂的片上系统(SoC)的嵌入式系统解决方案,以满足市场对低成本、低能耗的高性能的期望。嵌入式系统的内存架构强烈地影响着关键的系统设计目标,如面积、功耗和性能。因此,嵌入式系统设计人员执行完整的内存体系结构探索,为给定的一组应用程序定制设计内存体系结构。此外,设计师会对多个优化设计点感兴趣,以满足不同的细分市场。然而,严格的上市时间限制强制缩短了设计周期。在本文中,我们通过结合基于穷尽搜索的外部存储器探索和基于两步的基于SPRAM-Cache的内部结构的集成数据布局来解决多层次多目标存储器体系结构探索问题。我们提出了一种基于SPRAM-Cache混合架构的数据布局的两步集成方法,第一步是数据分区,在SPRAM和Cache之间划分数据,第二步是缓存感知数据布局。我们将缓存敏感的数据布局表述为一个图分区问题,并表明我们的方法比现有方法提高了34%,并且还优化了片外内存地址空间。我们用3个嵌入式多媒体应用程序试验了我们的方法,我们的方法为每个应用程序探索了几百个内存配置,在标准桌面上的几个小时的计算中产生了几个最佳设计点。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.
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