A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits

Abstract

Soft-errors are a leading cause of reliability issues during field operations. High-energy particles, either from cosmic rays or from impurities in the packaging material can disrupt charge stored on the internal node capacitances leading to a malfunction of the device. Although this is usually a temporary effect, it may lead to Silent Data Corruption(SDC) when not detected in time. SDC may be detrimental to many real-time commercial applications of the device and demands an effective solution that is cheap in terms of various design overheads. In this paper, we propose two novel flip-flop designs aimed at detecting and correcting soft-errors and transients from combinational circuits.Each design is optimized for a different set of constraints and they have area overheads of 40% and 21% as compared to the standard industrial design of a scan flip- flop.