基于混合纳米- cmos结构的容错计算

M. O. Simsir, S. Cadambi, Franjo Ivancic, M. Rötteler, N. Jha
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引用次数: 5

摘要

基于纳米级分子器件的体系结构正在引起人们的关注,以取代半导体路线图末端的CMOS体系结构。根据ITRS的说法,两种最有前途的纳米技术是硅纳米线和碳纳米管。尽管它们为构建逻辑、互连和内存提供了无与伦比的密度,但它们的制造过程非常容易出现缺陷。这进一步加剧了测试的复杂性,因为几乎不可能检测到大型纳米级芯片中的所有缺陷。此外,纳米结构中的小结构容易受到瞬态故障的影响,从而产生任意的软误差。因此,容错是使纳米级架构实用和现实的必要条件。我们提出了一种能够容忍大量未检测到的制造故障和大量瞬态故障的体系结构。我们的体系结构的特点是多级冗余和多数投票,以纠正由此类错误引起的错误。该架构的一个关键方面是,它包含了纳米级和传统CMOS组件的明智平衡。与该体系结构配套的是一个编译器,该编译器具有经过定制的启发式,可以快速而紧凑地将逻辑映射到部分有缺陷的组件上。实验结果证明了该结构的有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture
Architectures based on nanoscale molecular devices are attracting attention for replacing CMOS architectures at the end of the semiconductor roadmap. The two most promising nanotechnologies, according to ITRS, are silicon nanowires and carbon nanotubes. Although they offer unmatched densities for building logic, interconnect and memory, they suffer from very defect-prone manufacturing processes. This is further exacerbated by testing complexities where it is nearly impossible to detect all defects in a large nanoscale chip. Furthermore, the small structures in nanoscale architectures are susceptible to transient faults which can produce arbitrary soft errors. As a result, fault tolerance is necessary to make nanoscale architectures practical and realistic. We propose an architecture that can tolerate a large number of undetected manufacturing faults as well as a large rate of transient faults. Our architecture is characterized by multiple levels of redundancy and majority voting to correct errors caused by such faults. A key aspect of the architecture is that it contains a judicious balance of both nanoscale and traditional CMOS components. A companion to the architecture is a compiler with heuristics tailored to quickly and compactly map logic onto partially defective components. Experimental results demonstrate the efficacy of the architecture.
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