1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)最新文献

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Laser beam carrier injection technique for CMOS LSI failure analysis using an OBIC: light-induced state transition (LIST) method 基于OBIC的激光载流子注入技术用于CMOS LSI失效分析:光致态跃迁(LIST)方法
Y. Kohno, M. Shimizu, K. Kitamura, A. Nishikawa, C. Odani, N. Miura
{"title":"Laser beam carrier injection technique for CMOS LSI failure analysis using an OBIC: light-induced state transition (LIST) method","authors":"Y. Kohno, M. Shimizu, K. Kitamura, A. Nishikawa, C. Odani, N. Miura","doi":"10.1109/ISSM.1997.664592","DOIUrl":"https://doi.org/10.1109/ISSM.1997.664592","url":null,"abstract":"This paper describes a new technique, called the Light-Induced State Transition (LIST) method that uses an optical beam induced current (OBIC) system for failure analysis of CMOS LSIs. This technique allows one to locate a low signal line short-circuited to a GND bus (or a high signal line short-circuited to a V/sub DD/ bus) in stand-by condition which is not possible with conventional failure analysis techniques such as photo-emission analysis, liquid crystal technique, or the conventional OBIC method. The effectiveness of the LIST method was verified by an experiment on inverter chains that included quasi-failures intentionally patched by FIB deposition. The LIST method has also been used for actual CMOS logic failure analysis, and has proved to be useful for finding a failure location rapidly.","PeriodicalId":138267,"journal":{"name":"1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)","volume":"639 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120846648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Effective multi-stage test equipment capacity allocation for semiconductor fabrication yield enhancement 提高半导体制造良率的有效多级测试设备容量分配
K.D. Chen, R. Akella, I. Emami, M. McIntyre
{"title":"Effective multi-stage test equipment capacity allocation for semiconductor fabrication yield enhancement","authors":"K.D. Chen, R. Akella, I. Emami, M. McIntyre","doi":"10.1109/ISSM.1997.664628","DOIUrl":"https://doi.org/10.1109/ISSM.1997.664628","url":null,"abstract":"We formulate a multi-stage inspection planning model based on configurations in actual semiconductor fab-lines, specifically taking into account both the capacity constraint and the congestion effects at the inspection station. We propose a new mixed First-Come-First-Serve (FCFS) and Last-Come-First-Serve (LCFS) discipline for serving the inspection samples to expedite the detection of potential yield problems. Employing this mixed FCFS and LCFS discipline, we derive approximate expressions for the queueing delays in yield problem detection time and develop near-optimal algorithms to obtain the inspection logistics planning policies.","PeriodicalId":138267,"journal":{"name":"1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125671308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Diluted wet oxidation: a novel technique for ultra thin gate oxide formation 稀释湿氧化:超薄栅氧化形成的新技术
Y. Tanabe, Y. Nakatsuka, S. Sakai, T. Miyazaki, T. Nagahama
{"title":"Diluted wet oxidation: a novel technique for ultra thin gate oxide formation","authors":"Y. Tanabe, Y. Nakatsuka, S. Sakai, T. Miyazaki, T. Nagahama","doi":"10.1109/ISSM.1997.664621","DOIUrl":"https://doi.org/10.1109/ISSM.1997.664621","url":null,"abstract":"An ultra-pure water vapor generator that is compatible with RTP wet oxidation has been developed to meet the need for high quality gate oxides in deep sub-micron device process. This generator is based on a catalytic surface reaction of hydrogen gas and oxygen gas, and enables a precise control of H/sub 2/O/O/sub 2/ ratio in the processing gas at any desired percentage. Diluted Wet Oxidation (DWO) utilizes a low H/sub 2/O/O/sub 2/ ratio precisely controlled by the water vapor generator to obtain a low oxidation rate comparable to dry oxidation, which results in an accurate film thickness while maintaining the film characteristics of wet oxidation.","PeriodicalId":138267,"journal":{"name":"1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123501243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Market and technology outlook into the year 2000 [semiconductor manufacturing] 进入2000年的市场与技术展望[半导体制造业]
T. Makimoto
{"title":"Market and technology outlook into the year 2000 [semiconductor manufacturing]","authors":"T. Makimoto","doi":"10.1109/ISSM.1997.664478","DOIUrl":"https://doi.org/10.1109/ISSM.1997.664478","url":null,"abstract":"Technological improvements to make fine geometries have been one of the key factors in developing high-performance, low-power, and highly integrated semiconductor devices, which have led to produce high-performance, low-power portable, electronic equipment. This trend in electronic equipment has been changing our daily lifestyle which in turn is driving demand for further improvements in semiconductor devices. However, as geometry becomes finer, the amount of investment required to manufacture semiconductors is escalating. This paper discusses market outlook beyond the year 2000, and reviews enabling technologies. A new figure of merit is discussed which provides a guiding principle for technological progress in the new age, which the author calls the nomadic age.","PeriodicalId":138267,"journal":{"name":"1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116682206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Managing overall equipment effectiveness [OEE] to optimize factory performance 管理整体设备效率,优化工厂绩效
T. Pomorski
{"title":"Managing overall equipment effectiveness [OEE] to optimize factory performance","authors":"T. Pomorski","doi":"10.1109/ISSM.1997.664488","DOIUrl":"https://doi.org/10.1109/ISSM.1997.664488","url":null,"abstract":"Overall equipment effectiveness (OEE) is the key metric of total productive manufacturing (TPM). OEE monitors the actual performance of a tool relative to its performance capabilities under optimal manufacturing conditions. OEE looks at the entire manufacturing environment measuring, not only the equipment availability, but also, the production efficiency while the equipment is available to run product, as well as the efficiency loss that results from scrap, rework, and yield losses. Analysis of the equipment effectiveness loss mechanisms provides the user with improvement opportunities for the operation. This paper focuses on the use of OEE and major equipment loss analysis to optimize the performance of constraint tools at Fairchild Semiconductor, South Portland, Maine. Factory modeling is a key element of the OEE management process, defining the equipment and process capabilities at the workstation (micro) level, then identifying constraint tools and OEE performance requirements through macro level factory capacity modeling. Also discussed in this paper, is the SEMI productivity metrics standard proposal which defines OEE and loss analysis methods which are consistent with SEMI E10-96 concepts.","PeriodicalId":138267,"journal":{"name":"1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126280575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
A tight flow control for job-shop fabrication lines with finite buffers 有限缓冲作业车间生产线的严密流量控制
H. Toba
{"title":"A tight flow control for job-shop fabrication lines with finite buffers","authors":"H. Toba","doi":"10.1109/ISSM.1997.664532","DOIUrl":"https://doi.org/10.1109/ISSM.1997.664532","url":null,"abstract":"We propose WIP estimation how control method which serves as a countermeasure against the evaluating timelag problem and the throughput degradation problem with the conventional flow control method (push-pull method). The most important features of this method are: (1) how control based on WIP estimation and scheduling, (2) the breaking down of the entire schedule into individual lot schedules, and (3) greedy lot scheduling for contiguous finite buffers. In actual LCD fabrication line simulation we have confirmed that WIP estimation method is a promising one from the standpoint of line throughput obtained with.","PeriodicalId":138267,"journal":{"name":"1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126021446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Integrated test facility (ITF)-automation testing to support Intel's manufacturing output 集成测试设施(ITF)-自动化测试,以支持英特尔的制造输出
J. Bisgrove, R. Dayao, B. Houser, T. Jones, J. Mayes, M. McGinnis, M. Schmidt, G. Skyles, B. K. Tan
{"title":"Integrated test facility (ITF)-automation testing to support Intel's manufacturing output","authors":"J. Bisgrove, R. Dayao, B. Houser, T. Jones, J. Mayes, M. McGinnis, M. Schmidt, G. Skyles, B. K. Tan","doi":"10.1109/ISSM.1997.664526","DOIUrl":"https://doi.org/10.1109/ISSM.1997.664526","url":null,"abstract":"To meet the challenges of increasing automation and the potential for downtime, the current Virtual Factory Joint Automation Managers (JAM) worked with Components Automation Systems (CAS), the central engineering group responsible for the automation system, to create an Integrated Test Facility (ITF). ITF's mission is to conduct volume integrated testing of the automation suite prior to production release and to ensure that the automation suite does not hinge factory ramp. The ITF is a complete factory automation system running simulated production wafers. Established in January 1996, the ITF tests new automation product changes integrated into a complete factory manufacturing automation system and certifies that they can run in high volume. Integrated with CAS automation processes, the ITF is a key part of a process that delivers quality software.","PeriodicalId":138267,"journal":{"name":"1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127317718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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