A tight flow control for job-shop fabrication lines with finite buffers

Abstract

We propose WIP estimation how control method which serves as a countermeasure against the evaluating timelag problem and the throughput degradation problem with the conventional flow control method (push-pull method). The most important features of this method are: (1) how control based on WIP estimation and scheduling, (2) the breaking down of the entire schedule into individual lot schedules, and (3) greedy lot scheduling for contiguous finite buffers. In actual LCD fabrication line simulation we have confirmed that WIP estimation method is a promising one from the standpoint of line throughput obtained with.