2013 IEEE International Reliability Physics Symposium (IRPS)最新文献

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GaN-HEMTs devices with single- and double-heterostructure for power switching applications 用于功率开关应用的单双异质gan - hemt器件
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6531983
G. Meneghesso, A. Zanandrea, A. Stocco, I. Rossetto, C. de Santi, F. Rampazzo, M. Meneghini, E. Zanoni, Eldad Bahat Treidel, O. Hilt, P. Ivo, J. Wuerfl
{"title":"GaN-HEMTs devices with single- and double-heterostructure for power switching applications","authors":"G. Meneghesso, A. Zanandrea, A. Stocco, I. Rossetto, C. de Santi, F. Rampazzo, M. Meneghini, E. Zanoni, Eldad Bahat Treidel, O. Hilt, P. Ivo, J. Wuerfl","doi":"10.1109/IRPS.2013.6531983","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531983","url":null,"abstract":"We report on an extensive study of single- (SH) and double-heterostructure (DH) HEMTs based on gallium nitride, for power switching applications. The analysis is based on dc, pulsed and breakdown measurements, which were carried out on five different epitaxial structures.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129805673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Electromigration early failure void nucleation and growth phenomena in Cu and Cu(Mn) interconnects Cu和Cu(Mn)互连中电迁移早期失效空穴成核和生长现象
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6531951
M. Hauschildt, C. Hennesthal, G. Talut, O. Aubel, M. Gall, K. Yeap, E. Zschech
{"title":"Electromigration early failure void nucleation and growth phenomena in Cu and Cu(Mn) interconnects","authors":"M. Hauschildt, C. Hennesthal, G. Talut, O. Aubel, M. Gall, K. Yeap, E. Zschech","doi":"10.1109/IRPS.2013.6531951","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531951","url":null,"abstract":"Electromigration early failure void nucleation and growth phenomena were studied using large-scale, statistical analysis methods. A total of about 496,000 interconnects were tested over a wide current density and temperature range (j = 3.4 to 41.2 mA/μm2, T = 200 to 350°C) to analyze the detailed behavior of the current density exponent n and the activation energy Ea. The results for the critical V1M1 downstream interface indicate a reduction from n = 1.55±0.10 to n = 1.15±0.15 when lowering the temperature towards 200°C for Cu-based interconnects. This suggests that the electromigration downstream early failure mechanism is shifting from a mix of nucleation-controlled (n = 2) and growth-controlled (n = 1) to a fully growth-controlled mode, assisted by the increased thermal stress at lower temperatures (especially at use conditions). For Cu(Mn)-based interconnects, a drop from n = 2.00±0.07 to n = 1.64±0.2 was found, indicating additional effects of a superimposed incubation time. Furthermore, at lower current densities, the Ea value seems to drop for both Cu and Cu(Mn) interconnects by a slight, but significant amount of 0.1 - 0.2eV. Implications for extrapolations of accelerated test data to use conditions are discussed. Furthermore, the scaling behavior of the early failure population at the NSD=-3 level (F~0.1%) was analyzed, spanning 90, 65, 45, 40 and 28 nm technology nodes.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"2018 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117007211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
An experimental methodology for the in-situ observation of the time-dependent dielectric breakdown mechanism in Copper/low-k on-chip interconnect structures 铜/低k片上互连结构中随时间变化的介电击穿机制的原位观察实验方法
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6531966
K. Yeap, M. Gall, C. Sander, S. Niese, Z. Liao, Y. Ritz, R. Rosenkranz, U. Muhle, J. Gluch, E. Zschech, O. Aubel, A. Beyer, C. Hennesthal, M. Hauschildt, G. Talut, J. Poppe, N. Vogel, H. Engelmann, D. Stauffer, R. Major, O. Warren
{"title":"An experimental methodology for the in-situ observation of the time-dependent dielectric breakdown mechanism in Copper/low-k on-chip interconnect structures","authors":"K. Yeap, M. Gall, C. Sander, S. Niese, Z. Liao, Y. Ritz, R. Rosenkranz, U. Muhle, J. Gluch, E. Zschech, O. Aubel, A. Beyer, C. Hennesthal, M. Hauschildt, G. Talut, J. Poppe, N. Vogel, H. Engelmann, D. Stauffer, R. Major, O. Warren","doi":"10.1109/IRPS.2013.6531966","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531966","url":null,"abstract":"This study captures the time-dependent dielectric breakdown kinetics in nanoscale Cu/low-k interconnect structures, applying in-situ transmission electron microscopy (TEM) imaging and post-mortem electron spectroscopic imaging (ESI). A “tip-to-tip” test structure and an experimental methodology were established to observe the localized damage mechanisms under a constant voltage stress as a function of time. In an interconnect structure with partly breached barriers, in-situ TEM imaging shows Cu nanoparticle formation, agglomeration and movement in porous organosilicate glasses. In a flawless interconnect structure, in-situ TEM imaging and ESI mapping show close to no evidence of Cu diffusion in the TDDB process. From the ESI mapping, only a narrow Cu trace is found at the SiCN/OSG interface. In both cases, when barriers are breached or still intact, the initial damage is observed at the top interface of M1 between SiCN and OSG.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117050761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Self-heat reliability considerations on Intel's 22nm Tri-Gate technology 对英特尔22nm三栅极技术的自热可靠性考虑
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6532036
C. Prasad, L. Jiang, D. Singh, M. Agostinelli, C. Auth, P. Bai, T. Eiles, J. Hicks, C. Jan, K. Mistry, S. Natarajan, B. Niu, P. Packan, D. Pantuso, I. Post, S. Ramey, A. Schmitz, B. Sell, S. Suthram, J. Thomas, C. Tsai, P. Vandervoorn
{"title":"Self-heat reliability considerations on Intel's 22nm Tri-Gate technology","authors":"C. Prasad, L. Jiang, D. Singh, M. Agostinelli, C. Auth, P. Bai, T. Eiles, J. Hicks, C. Jan, K. Mistry, S. Natarajan, B. Niu, P. Packan, D. Pantuso, I. Post, S. Ramey, A. Schmitz, B. Sell, S. Suthram, J. Thomas, C. Tsai, P. Vandervoorn","doi":"10.1109/IRPS.2013.6532036","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532036","url":null,"abstract":"This paper describes various measurements on self-heat performed on Intel's 22nm process technology, and outlines its reliability implications. Comparisons to thermal modeling results and analytical data show excellent matching.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123292287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 98
Impact of cell distance and well-contact density on neutron-induced Multiple Cell Upsets 细胞距离和孔接触密度对中子诱导的多细胞扰动的影响
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1587/TRANSELE.E98.C.298
J. Furuta, Kazutoshi Kobayashi, H. Onodera
{"title":"Impact of cell distance and well-contact density on neutron-induced Multiple Cell Upsets","authors":"J. Furuta, Kazutoshi Kobayashi, H. Onodera","doi":"10.1587/TRANSELE.E98.C.298","DOIUrl":"https://doi.org/10.1587/TRANSELE.E98.C.298","url":null,"abstract":"We measured neutron-induced Single Event Upsets (SEUs) and Multiple Cell Upsets (MCUs) on Flip-Flops (FFs) in a 65 nm bulk CMOS process. Measurement results show that MCU / SEU is up to 23.4% and is exponentially decreased by the distance between latches on FFs. MCU rates can drastically be reduced by inserting well-contact arrays between FFs. The number of MCUs is reduced from 110 to 1 by inserting a well-contact array under power and ground rails.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"175 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123401924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Short line electromigration characteristics and their applications for circuit design 短线电迁移特性及其在电路设计中的应用
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6532000
Baozhen Li, C. Christiansen, C. Burke, N. Hogle, D. Badami
{"title":"Short line electromigration characteristics and their applications for circuit design","authors":"Baozhen Li, C. Christiansen, C. Burke, N. Hogle, D. Badami","doi":"10.1109/IRPS.2013.6532000","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532000","url":null,"abstract":"Technology scaling has led to severe electromigration degradation for advanced interconnects. Taking full advantage of the Blech effect benefit has become more and more important for circuit design to overcome this EM performance degradation. Due to the wide range of circuit design layout variations, understanding the EM characteristics of the short lines closely related to the real circuit and chip design applications is needed. In this study, EM characteristics of a wide range of different short line structures are investigated. These structures include simple short line segments, short line segments with branches and with passive passing lines on top, and long lines with only a short portion carrying current. Implications of these results to circuit and chip design are also discussed.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"34 30","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120813579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Electromigration extrusion kinetics of Cu interconnects 铜互连的电迁移挤出动力学
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6531954
Lijuan Zhang, Ping-Chuan Wang, Xiao Hu Liu, P. McLaughlin, R. Filippi, Baozhen Li, J. Bao
{"title":"Electromigration extrusion kinetics of Cu interconnects","authors":"Lijuan Zhang, Ping-Chuan Wang, Xiao Hu Liu, P. McLaughlin, R. Filippi, Baozhen Li, J. Bao","doi":"10.1109/IRPS.2013.6531954","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531954","url":null,"abstract":"Electromigration lifetime and failure mechanism have been investigated for Cu/low-k interconnects at intermediate interconnect levels. It was observed that extrusion fails occurred mostly before resistance shift fails were detected. The activation energy for extrusion fails was determined to be 1.13 eV, comparable to the value of 0.99 eV for the resistance shift fails. This suggests the same failure mechanism for two failure modes: Cu mass transport primarily along the Cu/cap interface. The current exponent was extracted as 1.48 and 1.36 for extrusion fails and resistance shift fails, respectively. Physical failure analysis confirmed Cu extrusion near the anode and void formation at the cathode. Samples with improved pre-clean process before the cap deposition significantly suppressed EM induced extrusions, indicating a mechanically stronger Cu/cap interface. Furthermore, effective atomic sink at the anode end appeared to reduce the compressive stress buildup during EM, as it also significantly mitigated EM induced extrusion.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123684940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process 一种高性能体平面20nm替代栅高k金属栅技术的固有介电堆可靠性及与28nm栅首高k金属栅工艺的比较
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6532016
W. McMahon, C. Tian, S. Uppal, H. Kothari, M. Jin, G. Larosa, T. Nigam, A. Kerber, B. Linder, E. Cartier, W. Lai, Y. Liu, R. Ramachandran, U. Kwon, B. Parameshwaran, S. Krishnan, V. Narayanan
{"title":"Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process","authors":"W. McMahon, C. Tian, S. Uppal, H. Kothari, M. Jin, G. Larosa, T. Nigam, A. Kerber, B. Linder, E. Cartier, W. Lai, Y. Liu, R. Ramachandran, U. Kwon, B. Parameshwaran, S. Krishnan, V. Narayanan","doi":"10.1109/IRPS.2013.6532016","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532016","url":null,"abstract":"We compare the intrinsic reliability of the dielectric stack of a high performance bulk planar 20nm replacement gate technology to the reliability of high performance bulk planar 28 nm gate first high-k metal gate (HKMG) technology, developed within the IBM Alliance. Comparable N/PFET TDDB and comparable/improved NFET PBTI are shown to be achievable for similar Tinv. The choice to not include channel silicon germanium as a PFET performance element in the 20nm technology impact NBTI, driving a potential tradeoff between NBTI and PBTI. The complexity of integrating such performance elements while accounting for reliability/performance tradeoffs demands their selection during technology definition with due consideration to realistic product usage conditions.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126645276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Evaluation of constant voltage testing for electromigration study 恒压试验对电迁移研究的评价
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6532078
Z. Zhang, B. McGowan, Z. Feldmaier, J. Lloyd, T. McMullen, E. Wilcox, S. Schultz
{"title":"Evaluation of constant voltage testing for electromigration study","authors":"Z. Zhang, B. McGowan, Z. Feldmaier, J. Lloyd, T. McMullen, E. Wilcox, S. Schultz","doi":"10.1109/IRPS.2013.6532078","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532078","url":null,"abstract":"Constant voltage electromigration testing (CV) was evaluated to be a complementary method to traditional constant current (CC) testing during electromigration (EM) qualification. It is demonstrated that the EM lifetime in copper conductors could vary depending on the details of the circuit. There is also a difference in failure distribution and possibly in failure modes as well. Furthermore, the constant voltage test was used to probe the lifetime dependency on location and for investigating redundancy. The experiments showed non negligible differences in both types of test and it is concluded that further failure analysis required for confirming and/or understanding the differences in the observations.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"2011 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114624934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A junction leakage mechanism and its effects on advance SRAM failure 结漏机制及其对SRAM提前失效的影响
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6531994
D. Maji, P. Liao, Y. Lee, J. Shih, S. C. Chen, S. Gao, J. H. Lee, K. Wu
{"title":"A junction leakage mechanism and its effects on advance SRAM failure","authors":"D. Maji, P. Liao, Y. Lee, J. Shih, S. C. Chen, S. Gao, J. H. Lee, K. Wu","doi":"10.1109/IRPS.2013.6531994","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531994","url":null,"abstract":"Junction leakage is becoming an important reliability concern as shallow trench isolation (STI) continues to scale down. This junction leakage has to be considered to improve SRAM Vccmin degradation. The major index of junction leakage in SRAM cell is found to be off-state leakage current as the leakage phenomenon externally manifests as a current flow from butted contact (BCT) to lower pull down (LPD) transistor gate. Isolation test patterns (P+/N-well to P-Well) with well photo misalignments are designed to verify Si/STI interface damage effect on junction leakage. Process experiment with PW misalignment shows isolation leakage current (P+ to PW) increase after electrical stress. However, this type of leakage due to PW misalignment shows weak temperature and voltage dependence, indicating that the trap-assisted carrier hopping at STI Si/SiO2 interface and the PW misalignment are paramount of SRAM junction reliability. Using TCAD simulation, we have verified that carriers transport through the Si/STI interface traps along with poor PW misalignment is the root causes of the junction leakage current increase. HSPICE simulation results show that junction leakage worsen SRAM cell stability by degrading SRAM read margin (SNM) and may eventually lead to cell failure.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115890784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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