2013 IEEE International Reliability Physics Symposium (IRPS)最新文献

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ESD in FinFET technologies: Past learning and emerging challenges ESD在FinFET技术:过去的学习和新出现的挑战
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6531950
D. Linten, G. Hellings, Shih-Hung Chen, G. Groeseneken
{"title":"ESD in FinFET technologies: Past learning and emerging challenges","authors":"D. Linten, G. Hellings, Shih-Hung Chen, G. Groeseneken","doi":"10.1109/IRPS.2013.6531950","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531950","url":null,"abstract":"FinFET technologies were seen as a potential roadblock for providing high ESD reliable ICs due to the 3D nature of the narrow Si fins which do not allow a large current conduction before thermal failure. However, a detailed assessment of common ESD structures such as diodes and grounded gate devices, has shown that ESD reliability is not a roadblock for finFET-based products. Studying both SOI and bulk FinFETs, bulk FinFET was found to provide superior ESD performance due to the fin connection to the substrate. Focusing on sub-20-nm bulk FinFET technologies, emerging challenges are not limited to dealing with the smaller silicon volume of the fins and finer pitch, but also with the introduction of high mobility channels in the fins. The introduction of these materials can have a profound impact on the intrinsic ESD performance and must therefore be studied. In this work we will present past learning on ESD protection devices in FinFET technologies, for SOI and bulk FinFETs, TCAD methods used to analyze the ESD results, and we will present the results for non-silicon FinFET technologies which are being considered for the 14 and 10-nm CMOS nodes.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"283 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116854951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Estimation of hardened flip-flop neutron soft error rates using SRAM multiple-cell upset data in bulk CMOS 基于块体CMOS中SRAM多单元扰动数据的硬化触发器中子软错误率估计
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6532113
N. Gaspard, S. Jagannathan, Z. Diggins, M. Mccurdy, T. D. Loveless, B. Bhuva, L. Massengill, W. T. Holman, T. Oates, Y. Fang, S. Wen, R. Wong, K. Lilja, M. Bounasser
{"title":"Estimation of hardened flip-flop neutron soft error rates using SRAM multiple-cell upset data in bulk CMOS","authors":"N. Gaspard, S. Jagannathan, Z. Diggins, M. Mccurdy, T. D. Loveless, B. Bhuva, L. Massengill, W. T. Holman, T. Oates, Y. Fang, S. Wen, R. Wong, K. Lilja, M. Bounasser","doi":"10.1109/IRPS.2013.6532113","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532113","url":null,"abstract":"Experimental neutron single-event error rates of 28-and 40-nm bulk CMOS hardened flip-flops are compared to various hardened flip-flop designs in literature. Using published 45-nm SRAM multiple-cell upset data, it is shown that the error rate of hardened flip-flop designs can be estimated by using the minimum sensitive node spacing from the flip-flop layout. Experimental data show that regardless of circuit topology of a hardened flip-flop, the redundant storage node spacing dominates neutron soft-error rates.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126192016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
TOF-SIMS characterization of Boron and phosphorus distribution in sub-atmospheric chemical vapour deposition borophosphosilicate glass (SA-CVD BPSG) films 亚大气化学气相沉积硼磷硅酸盐玻璃(SA-CVD BPSG)薄膜中硼磷分布的TOF-SIMS表征
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6532026
E. Ferlito, G. Pizzo, R. de Gregorio, G. Anastasi, R. Ricciari, D. Mello
{"title":"TOF-SIMS characterization of Boron and phosphorus distribution in sub-atmospheric chemical vapour deposition borophosphosilicate glass (SA-CVD BPSG) films","authors":"E. Ferlito, G. Pizzo, R. de Gregorio, G. Anastasi, R. Ricciari, D. Mello","doi":"10.1109/IRPS.2013.6532026","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532026","url":null,"abstract":"Deposition of BPSG films as dielectrics is a critical step in semiconductor device manufacturing. Accurate control of concentration depth profile of Boron and Phosphorus in BPSG is important, because these variables determine the performance and reliability of the dielectric film. In this study, a method to characterize BPSG films using TOF-SIMS is shown. A failure analysis case study in which TOF-SIMS characterization allows correlating Tungsten extrusion with non-uniform dopant distribution is presented.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126484771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reliability characteristics of thin porous low-K silica-based interconnect dielectrics 薄多孔低钾硅基互连介质的可靠性特性
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6531968
Y. Barbarin, K. Croes, P. Roussel, Y. Li, P. Verdonck, M. Baklanov, Z. Tokei, L. Zhao
{"title":"Reliability characteristics of thin porous low-K silica-based interconnect dielectrics","authors":"Y. Barbarin, K. Croes, P. Roussel, Y. Li, P. Verdonck, M. Baklanov, Z. Tokei, L. Zhao","doi":"10.1109/IRPS.2013.6531968","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531968","url":null,"abstract":"The dielectric breakdown field (EBD) and the time-dependent-dielectric-breakdown (TDDB) of eight different low-K films with porosities between 3% (K=3.2) and 50% (K=1.8) and thicknesses between 15 and 60 nm were investigated using imec's planar capacitors (p-cap) test vehicle. EBD values decrease linearly with porosity to reach 6MV/cm at 50% porosity. The analogous Organo-Silicate Glass (OSG) films show a similar field acceleration factors independently of porosity. An OSG 2.0 film with 45% porosity and a periodic mesoporous organosilica (PMO) 1.8 film, both sealed with 12-nm OSG 3.0 sealing also showed the same field acceleration factor. On the other hand, the corresponding Weibull slopes vary and decrease linearly with porosity, which is in agreement with the percolation model. Also, the Weibull slopes decrease linearly with dielectric thickness. Extrapolating those data and analyzing the maximum allowed electrical fields to meet 10-years lifetime (EMAX), critical dielectric spacing are discussed as a function of porosity. It is shown that for 20-nm spacing remedial measures are required for porosities >30%.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125739632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Space radiation and reliability qualifications on 65nm CMOS 600MHz microprocessors 65nm CMOS 600MHz微处理器的空间辐射和可靠性鉴定
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6532051
S. Clerc, F. Abouzeid, G. Gasiot, J. Daveau, C. Bottoni, M. Glorieux, J. Autran, F. Cacho, V. Huard, L. Dugoujon, R. Weigand, F. Malou, L. Hili, P. Roche
{"title":"Space radiation and reliability qualifications on 65nm CMOS 600MHz microprocessors","authors":"S. Clerc, F. Abouzeid, G. Gasiot, J. Daveau, C. Bottoni, M. Glorieux, J. Autran, F. Cacho, V. Huard, L. Dugoujon, R. Weigand, F. Malou, L. Hili, P. Roche","doi":"10.1109/IRPS.2013.6532051","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532051","url":null,"abstract":"Recent space programs have reached the limits of the current space digital ASIC offers, mainly relying on CMOS 180nm. The new ST CMOS 65nm space program described in this paper shows how those limits are overcome. Small modifications to the commercial bulk process, paired with cost effective design reinforcements allow higher density and better energy efficiency while ensuring a strong space-grade resilience. The implementation of a 32-bit SPARC LEON3 microprocessor demonstrates the capabilities of this new technology.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128207769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Experimental analyses of the mechanical reliability of advanced BEOL/fBEOL stacks regarding CPI loading 新型BEOL/fBEOL叠层在CPI载荷下的机械可靠性实验分析
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6532030
H. Geisler, E. Schuchardt, M. Brueckner, P. Hofmann, K. Machani, F. Kuechenmeister, D. Breuer, H. Engelmann
{"title":"Experimental analyses of the mechanical reliability of advanced BEOL/fBEOL stacks regarding CPI loading","authors":"H. Geisler, E. Schuchardt, M. Brueckner, P. Hofmann, K. Machani, F. Kuechenmeister, D. Breuer, H. Engelmann","doi":"10.1109/IRPS.2013.6532030","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532030","url":null,"abstract":"The introduction of fragile ultralow-k materials as interlayer dielectrics in backend-of-line interconnect stacks asks for a thorough analysis of potential risks due to chip-package interaction. This paper shows how the application of several ex-situ and in-situ experimental approaches can be effectively used to assess such risks on the wafer level already at early stages of the development phase. The respective analytical techniques try to mimic chip-package interaction loading conditions. Most of the tests transfer loads to interconnect stacks via individual copper pillars. The investigations take place on the scale of about 100μm down to 1μm.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121321831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Statistical assessment of endurance degradation in high and low resistive states of the HfO2-based RRAM 基于hfo2的RRAM在高、低电阻状态下耐力退化的统计评估
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6532093
S. Deora, G. Bersuker, M. Sung, D. Gilmer, P. Kirsch, H.-F Li, H. Chong, S. Gausepohl
{"title":"Statistical assessment of endurance degradation in high and low resistive states of the HfO2-based RRAM","authors":"S. Deora, G. Bersuker, M. Sung, D. Gilmer, P. Kirsch, H.-F Li, H. Chong, S. Gausepohl","doi":"10.1109/IRPS.2013.6532093","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532093","url":null,"abstract":"This study discusses variability of the high and low resistance states (HRS and LRS, respectively) during the pulse cycling of the cross-bar 1T1R HfO2 based RRAM devices. Read current variation in LRS is found to follow a normal distribution while in the HRS, it is described by the log-normal dependency. It has been identified that the endurance degradation primarily occurs due increasing resistance in LRS caused by the shrinkage of the filament size.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115958439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Effects of positive and negative constant voltage stress on organic TFTs 正负恒压应力对有机tft的影响
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6532123
N. Wrachien, A. Cester, D. Bari, G. Meneghesso, J. Kováč, J. Jakabovic, M. Weis, D. Donoval
{"title":"Effects of positive and negative constant voltage stress on organic TFTs","authors":"N. Wrachien, A. Cester, D. Bari, G. Meneghesso, J. Kováč, J. Jakabovic, M. Weis, D. Donoval","doi":"10.1109/IRPS.2013.6532123","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532123","url":null,"abstract":"We subjected Organic TFTs to positive and negative constant gate voltage stresses. Stress not only induces temporary charge trapping, but also permanent transconductance degradation. The permanent degradation is accelerated if the devices are stressed under illumination. Negative stress degrades the TFT much faster than the positive stress, at the same voltage. Furthermore, hard breakdowns are observed on devices stressed under light, with VGS= -65V. The degradation mainly comes from stress-induced interface trap generation, rather than photochemical reactions as observed with UV irradiations.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115968033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Accelerated stress testing methodology to risk assess silicon-package thermomechanical failure modes resulting from moisture exposure under use condition 用于评估在使用条件下因受潮而导致的硅封装热机械失效模式风险的加速应力测试方法
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6532032
S. Rangaraj, Daeil Kwon, M. Pei, J. Hicks, G. Leatherman, A. Lucero, T. Wilson, S. Streit, Jun He
{"title":"Accelerated stress testing methodology to risk assess silicon-package thermomechanical failure modes resulting from moisture exposure under use condition","authors":"S. Rangaraj, Daeil Kwon, M. Pei, J. Hicks, G. Leatherman, A. Lucero, T. Wilson, S. Streit, Jun He","doi":"10.1109/IRPS.2013.6532032","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532032","url":null,"abstract":"IC components are exposed to moisture and thermal cycles during chip-package-board assembly and in their end use conditions. Moisture exposure influences the mechanical integrity of silicon backend dielectrics, assembly/packaging materials and packages. Reliability performance under accelerated stresses that simulate use conditions are often a critical factor in choice of materials, processing options and design rules. A complete assessment of the cumulative environmental exposure from chip-package assembly, shipment/storage, board system assembly, through end-customer use is required to guarantee product performance and reliability. This paper will detail these end user environments and use failure mode/mechanism specific acceleration models to develop accurate accelerated life testing plans and requirements. These requirements will then be compared to JEDEC standards based requirements and a need for re-calibration of these standards to more appropriate temperatures and stress durations will be highlighted.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132738888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
ESD protection design with adjustable snapback behavior for 5-V application in 100nm CMOS process ESD保护设计,具有可调的回吸行为,适用于100nm CMOS工艺中的5v应用
2013 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2013-04-14 DOI: 10.1109/IRPS.2013.6532072
Chang-Tzu Wang, Yu-Chun Chen, Tien-Hao Tang, K. Su
{"title":"ESD protection design with adjustable snapback behavior for 5-V application in 100nm CMOS process","authors":"Chang-Tzu Wang, Yu-Chun Chen, Tien-Hao Tang, K. Su","doi":"10.1109/IRPS.2013.6532072","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532072","url":null,"abstract":"An N-channel electrostatic discharge (ESD) protection device with DNW sinker has been designed without latch-up risk for 5-V operating condition. With the DNW sinker, the NMOS snapback behavior can be restrained and the holding voltage can be increased. The proposed ESD protection device can sustain 3.6kV human-body-model (HBM) and 325V machine model (MM) ESD tests. With holding voltage of 6.4V, the latch-up test shows the immunity from 7.5V voltage test and 200-mA current test.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133383157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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