Space radiation and reliability qualifications on 65nm CMOS 600MHz microprocessors

Abstract

Recent space programs have reached the limits of the current space digital ASIC offers, mainly relying on CMOS 180nm. The new ST CMOS 65nm space program described in this paper shows how those limits are overcome. Small modifications to the commercial bulk process, paired with cost effective design reinforcements allow higher density and better energy efficiency while ensuring a strong space-grade resilience. The implementation of a 32-bit SPARC LEON3 microprocessor demonstrates the capabilities of this new technology.