N. Gaspard, S. Jagannathan, Z. Diggins, M. Mccurdy, T. D. Loveless, B. Bhuva, L. Massengill, W. T. Holman, T. Oates, Y. Fang, S. Wen, R. Wong, K. Lilja, M. Bounasser
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Estimation of hardened flip-flop neutron soft error rates using SRAM multiple-cell upset data in bulk CMOS
Experimental neutron single-event error rates of 28-and 40-nm bulk CMOS hardened flip-flops are compared to various hardened flip-flop designs in literature. Using published 45-nm SRAM multiple-cell upset data, it is shown that the error rate of hardened flip-flop designs can be estimated by using the minimum sensitive node spacing from the flip-flop layout. Experimental data show that regardless of circuit topology of a hardened flip-flop, the redundant storage node spacing dominates neutron soft-error rates.
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