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Proceedings. IEEE Lester Eastman Conference on High Performance Devices最新文献

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InP/InGaAs heterojunction bipolar transistors grown on Ge/P co-implanted InP substrates by metal-organic molecular beam epitaxy 金属-有机分子束外延在Ge/P共植入InP衬底上生长InP/InGaAs异质结双极晶体管
Proceedings. IEEE Lester Eastman Conference on High Performance Devices Pub Date : 2002-08-06 DOI: 10.1109/LECHPD.2002.1146758
W. J. Sung, R. Kopf, D. Werder, C. T. Liu, Y. K. Chen, J. Chen, E. J. Zhu, Mau-Chung Frank Chang
{"title":"InP/InGaAs heterojunction bipolar transistors grown on Ge/P co-implanted InP substrates by metal-organic molecular beam epitaxy","authors":"W. J. Sung, R. Kopf, D. Werder, C. T. Liu, Y. K. Chen, J. Chen, E. J. Zhu, Mau-Chung Frank Chang","doi":"10.1109/LECHPD.2002.1146758","DOIUrl":"https://doi.org/10.1109/LECHPD.2002.1146758","url":null,"abstract":"InP/InGaAs Heterojunction Bipolar Transistors (HBTs) have demonstrated excellent high-frequency performance and are widely used for optical fiber transmission. However, the current mesa HBT structure utilizes a very thick, highly doped n/sup +/InGaAs layer for the subcollector contact. This added mesa height makes multi-level interconnection processes more difficult, which impedes the capability of fabricating compact integrated circuits. In addition, InP has a much higher thermal conductivity than InGaAs, so heat dissipation may be a problem for densely packed circuits with the above structure. This paper reports on InP/InGaAs HBTs grown on Ge/P co-implanted substrates by Metal-Organic Molecular Beam Epitaxy (MOMBE). This embedded subcollector HBT structure offers several advantages for the fabrication of large-scale integrated circuits on InP substrates.","PeriodicalId":137839,"journal":{"name":"Proceedings. IEEE Lester Eastman Conference on High Performance Devices","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127267979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Epitaxial ternary and quaternary III-V antimonide substrates 外延三元和季III-V型锑衬底
Proceedings. IEEE Lester Eastman Conference on High Performance Devices Pub Date : 2002-08-06 DOI: 10.1109/LECHPD.2002.1146753
M. Malik, J. Cox, C.V. Sulima, S. Datta, A. N. Tata
{"title":"Epitaxial ternary and quaternary III-V antimonide substrates","authors":"M. Malik, J. Cox, C.V. Sulima, S. Datta, A. N. Tata","doi":"10.1109/LECHPD.2002.1146753","DOIUrl":"https://doi.org/10.1109/LECHPD.2002.1146753","url":null,"abstract":"Modified liquid-phase epitaxy (LPE) techniques can be adapted for the growth of relatively thick (50 to 500 micron) epitaxial layers of ternary and quaternary Ill-V antimonide alloys, including InAsSb, InGaSb, AlGaAsSb, InGaAsSb, and InAsSbP. These structures can function as 'virtual' substrates with adjustable lattice constants for epitaxy of various optoelectronic devices such as mid-infrared photodiodes. A variety of substrate structures can be realized either by effecting gradual, continuous compositional grading of thick epilayers, or by growing multilayers with abrupt but incremental compositional changes between adjacent layers. Both approaches can be combined with selective removal of the seeding substrate and wafer bonding techniques. Low-defect alloy substrates with increased functionality, and with lattice constants and bandgaps significantly different than available with binary compound wafers (e.g., InAs or GaSb), appear feasible.","PeriodicalId":137839,"journal":{"name":"Proceedings. IEEE Lester Eastman Conference on High Performance Devices","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125737798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Silicon tunnel diodes formed by proximity rapid thermal diffusion 由近距离快速热扩散形成的硅隧道二极管
Proceedings. IEEE Lester Eastman Conference on High Performance Devices Pub Date : 2002-08-06 DOI: 10.1109/LECHPD.2002.1146779
Jinli Wang, D. Wheeler, Yan Yan, Jialin Zhao, S. Howard, A. Seabaugh
{"title":"Silicon tunnel diodes formed by proximity rapid thermal diffusion","authors":"Jinli Wang, D. Wheeler, Yan Yan, Jialin Zhao, S. Howard, A. Seabaugh","doi":"10.1109/LECHPD.2002.1146779","DOIUrl":"https://doi.org/10.1109/LECHPD.2002.1146779","url":null,"abstract":"We demonstrate the first silicon tunnel diodes formed using proximity rapid thermal diffusion and spin-on diffusants. Room temperature peak-to-valley current ratio (PVR) of 2 is obtained at approximately 100 A/cm/sup 2/ peak current density. Secondary ion mass spectroscopy is used to compare proximity rapid thermal diffusion with rapid thermal diffusion from spin-coated diffusants in direct contact with a device wafer. The proximity rapid thermal diffusion approach provides a cleaner wafer surface for subsequent processing and yields tunnel diodes with good local uniformity.","PeriodicalId":137839,"journal":{"name":"Proceedings. IEEE Lester Eastman Conference on High Performance Devices","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125808853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
SiGe diffusion barriers for P-doped Si/SiGe resonant interband tunnel diodes 掺p Si/SiGe谐振带间隧道二极管的SiGe扩散势垒
Proceedings. IEEE Lester Eastman Conference on High Performance Devices Pub Date : 2002-08-06 DOI: 10.1109/LECHPD.2002.1146762
Niu Jin, A. T. Rice, Paul R. Berger, P. Thompson, P. Chi, D. Simons
{"title":"SiGe diffusion barriers for P-doped Si/SiGe resonant interband tunnel diodes","authors":"Niu Jin, A. T. Rice, Paul R. Berger, P. Thompson, P. Chi, D. Simons","doi":"10.1109/LECHPD.2002.1146762","DOIUrl":"https://doi.org/10.1109/LECHPD.2002.1146762","url":null,"abstract":"Si/SiGe resonant interband tunnel diodes (RITD) employing /spl delta/-doping spikes of P and B that demonstrate negative differential resistance (NDR) at room temperature are presented. Thin SiGe layers sandwiching the B /spl delta/-doping spike used to suppress B out-diffusion are discussed. Three structures were investigated in this study. Structure A, which employed a symmetrical 1 nm Si /4 nm Si/sub 0.6/Ge/sub 0.4//1 nm Si (1/4/1) spacer, showed a peak-to-valley current ratio (PVCR) of 2.7 after 1 minute annealing at 725/spl deg/C. Structure B with an asymmetrical 0 nm Si/4 nm Si/sub 0.6/Ge/sub 0.4//2 nm Si (0/4/2) spacer configuration showed a PVCR of 3.2 after 1 minute annealing at 800/spl deg/C. Structure C, which is the same as Structure B, except that a 1 nm Si/sub 0.6/Ge/sub 0.4/ cladding layer was grown below the B /spl delta/-layer, further improved PVCR to 3.6 after 1 minute annealing at 825/spl deg/C. Results clearly show that, by introducing SiGe layers to clad the B delta-doping layer, the B diffusion is suppressed during the post growth annealing, which raises the thermal budget. A higher RTA temperature appears to be more effective in eliminating defects and results in a lower valley current and higher PVCR.","PeriodicalId":137839,"journal":{"name":"Proceedings. IEEE Lester Eastman Conference on High Performance Devices","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128653272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
AlGaAsSb/InGaAs/AlGaAsSb metamorphic HEMTs
Proceedings. IEEE Lester Eastman Conference on High Performance Devices Pub Date : 2002-08-06 DOI: 10.1109/LECHPD.2002.1146770
R. Webster, A. Anwar, J. Heaton, K. Nichols, S. Duncan
{"title":"AlGaAsSb/InGaAs/AlGaAsSb metamorphic HEMTs","authors":"R. Webster, A. Anwar, J. Heaton, K. Nichols, S. Duncan","doi":"10.1109/LECHPD.2002.1146770","DOIUrl":"https://doi.org/10.1109/LECHPD.2002.1146770","url":null,"abstract":"Deep quantum well In/sub 0.8/Ga/sub 0.2/As/AlGaAsSb MHEMTs on GaAs are described. The step-graded AlGaAsSb strain-relief buffer layer provided a high-quality surface for growth of the MHEMT layers. AlGaAsSb barrier layers offer flexibility in choosing the channel composition and the barrier height. Typical Hall mobilities were 11,000 cm/sup 2//V-sec at 300 K for carrier concentrations of 2.4/spl times/10/sup 12/ cm/sup -2/. Extrinsic DC transconductance of 820 mS/mm was obtained for an MHEMT with a 0.15 /spl mu/m/spl times/64 /spl mu/m gate. Typical extrinsic unity current gain cutoff, f/sub t/, was 173 GHz with maximum frequency of oscillation, f/sub max/, of 474 GHz. Aside from layer growth, the MHEMTs were fabricated using only small changes from conventional GaAs PHEMT processing. This technology promises affordable production costs for high performance millimeter-wave low noise amplifiers.","PeriodicalId":137839,"journal":{"name":"Proceedings. IEEE Lester Eastman Conference on High Performance Devices","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121226666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Simulation, characterization and design of epitaxial emitter NPN 4H-SiC BJTs for amplifier applications 放大器外延发射极NPN 4H-SiC BJTs的仿真、表征与设计
Proceedings. IEEE Lester Eastman Conference on High Performance Devices Pub Date : 2002-08-06 DOI: 10.1109/LECHPD.2002.1146749
P. Losee, R. Gutmann, T. P. Chow, S. Ryu, A. Agarwal, J. Palmour
{"title":"Simulation, characterization and design of epitaxial emitter NPN 4H-SiC BJTs for amplifier applications","authors":"P. Losee, R. Gutmann, T. P. Chow, S. Ryu, A. Agarwal, J. Palmour","doi":"10.1109/LECHPD.2002.1146749","DOIUrl":"https://doi.org/10.1109/LECHPD.2002.1146749","url":null,"abstract":"We have analyzed the implementation of a 4H-SiC NPN high voltage BJT as a small signal amplifier transistor. From experimental characterization and intrinsic device modeling, we determined that the factors limiting performance are base transport considerations and an inefficient layout for high frequency applications. Approaches such as improving base transport and base series resistance are suggested in order to achieve 4H-SiC BJTs with UHF and lower microwave frequency capabilities. Using two-dimensional numerical simulations, we present an improvement on the existing design wherein the intrinsic device modeling suggests a unity gain frequency f/sub T/ of approximately 5 GHz.","PeriodicalId":137839,"journal":{"name":"Proceedings. IEEE Lester Eastman Conference on High Performance Devices","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121620864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Monte Carlo simulation of InGaAs/InAlAs HEMTs with a quantum correction potential 具有量子校正势的InGaAs/InAlAs hemt的Monte Carlo模拟
Proceedings. IEEE Lester Eastman Conference on High Performance Devices Pub Date : 2002-08-06 DOI: 10.1109/LECHPD.2002.1146756
Bo Wu, T. Tang
{"title":"Monte Carlo simulation of InGaAs/InAlAs HEMTs with a quantum correction potential","authors":"Bo Wu, T. Tang","doi":"10.1109/LECHPD.2002.1146756","DOIUrl":"https://doi.org/10.1109/LECHPD.2002.1146756","url":null,"abstract":"In Monte Carlo simulation of high electron mobility transistors (HEMTs), how to position the source and drain contacts will significantly affect the drain current. Unlike many Monte Carlo (MC) simulations of HEMTs in the past, in this work, the source and drain contacts are placed on the top of the caps as in the real device instead of on the side adjacent to the channel. In addition, to taking the quantum effects into consideration, the effective potential approach of quantum correction has been incorporated into our MC simulator. We have found that the simulated drain current is substantially increased compared to that of using the classical potential.","PeriodicalId":137839,"journal":{"name":"Proceedings. IEEE Lester Eastman Conference on High Performance Devices","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131794432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
RF and DC characteristics of low-leakage InAs/AlSb HFETs 低漏InAs/AlSb hfet的RF和DC特性
Proceedings. IEEE Lester Eastman Conference on High Performance Devices Pub Date : 2002-08-06 DOI: 10.1109/LECHPD.2002.1146781
B. Brar, G. Nagy, J. Bergman, G. Sullivan, P. Rowell, H. Lin, M. Dahlstrom, C. Kadow, M. Rodwell
{"title":"RF and DC characteristics of low-leakage InAs/AlSb HFETs","authors":"B. Brar, G. Nagy, J. Bergman, G. Sullivan, P. Rowell, H. Lin, M. Dahlstrom, C. Kadow, M. Rodwell","doi":"10.1109/LECHPD.2002.1146781","DOIUrl":"https://doi.org/10.1109/LECHPD.2002.1146781","url":null,"abstract":"InAs/AlSb HFETs with excellent RF and DC properties are reported. The drain currents are 750 mA/mm. with peak transconductance g/sub m/ of 1.1 S/mm. The gate leakage is below 1 nA//spl mu/m/sup 2/ for low gate bias. The threshold voltages of 0.25 /spl mu/m and 0.5 /spl mu/m gate-length devices are -2.5 and -1.5 V respectively, indicating short channel effects are present. Small-signal measurements on a 0.25 /spl mu/m gate-length device show f/sub /spl tau// of 120 GHz and f/sub max/ of 100 GHz at drain voltages below 0.4 V.","PeriodicalId":137839,"journal":{"name":"Proceedings. IEEE Lester Eastman Conference on High Performance Devices","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132589540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Reliability evaluation of AlGaN/GaN HEMTs grown on SiC substrate SiC衬底生长AlGaN/GaN hemt的可靠性评价
Proceedings. IEEE Lester Eastman Conference on High Performance Devices Pub Date : 2002-08-06 DOI: 10.1109/LECHPD.2002.1146785
C. Lee, L. Witkowski, M. Muir, H. Tserng, P. Saunier, H. Wang, J. Yang, M.A. Khan
{"title":"Reliability evaluation of AlGaN/GaN HEMTs grown on SiC substrate","authors":"C. Lee, L. Witkowski, M. Muir, H. Tserng, P. Saunier, H. Wang, J. Yang, M.A. Khan","doi":"10.1109/LECHPD.2002.1146785","DOIUrl":"https://doi.org/10.1109/LECHPD.2002.1146785","url":null,"abstract":"AlGaN/GaN HEMTs have achieved record output power densities at microwave frequencies; however, reliability of these devices is still a major concern. In this paper, the results of DC and RF stress tests at several drain voltages of passivated 75 /spl mu/m devices are discussed. After DC stress for 48 hours, negligible differences in IN and small signal performance were observed in some devices, while significant reduction in drain current, decrease in transconductance, and increase in on-resistance were measured in some other devices. RF stress for 40 hours has resulted in lower transconductance and drain current and degradation in power performance at 10 GHz. A comprehensive comparison of equivalent circuit models before and after stress is presented.","PeriodicalId":137839,"journal":{"name":"Proceedings. IEEE Lester Eastman Conference on High Performance Devices","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114344532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Three-dimensional integration in silicon electronics 硅电子学中的三维集成
Proceedings. IEEE Lester Eastman Conference on High Performance Devices Pub Date : 2002-08-06 DOI: 10.1109/LECHPD.2002.1146728
S. Tiwari, H. Kim, S. K. Kim, A. Kumar, C.C. Liu, L. Xue
{"title":"Three-dimensional integration in silicon electronics","authors":"S. Tiwari, H. Kim, S. K. Kim, A. Kumar, C.C. Liu, L. Xue","doi":"10.1109/LECHPD.2002.1146728","DOIUrl":"https://doi.org/10.1109/LECHPD.2002.1146728","url":null,"abstract":"As silicon electronics reaches length scales of 100 to 10 nm, device densities of 10/sup 9/ to 10/sup 11/ cm/sup -2/, interconnect densities of 10/sup 10/ to 10/sup 12/ cm/sup -2/, and applications across the spectrum of digital, analog, and mixed-signal domain, a number of key issues arise related to maintaining the improvement in performance, cost, power, and designability. Three-dimensional integration incorporating planar transistors offers interesting new directions for continuing improvements. Adaptive modifications of the planar transistors offer higher scalability and functionality, higher vertical interconnectivity in between device planes can reduce interconnect delays, higher programmability using configurable elements can provide efficient signal and energy flow, higher digital-analog isolation using ground-planes can provide cross-talk improvements for mixed-signal applications, and a power-aware design can allow control of temperature and power dissipation.","PeriodicalId":137839,"journal":{"name":"Proceedings. IEEE Lester Eastman Conference on High Performance Devices","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127317526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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