Three-dimensional integration in silicon electronics

Abstract

As silicon electronics reaches length scales of 100 to 10 nm, device densities of 10/sup 9/ to 10/sup 11/ cm/sup -2/, interconnect densities of 10/sup 10/ to 10/sup 12/ cm/sup -2/, and applications across the spectrum of digital, analog, and mixed-signal domain, a number of key issues arise related to maintaining the improvement in performance, cost, power, and designability. Three-dimensional integration incorporating planar transistors offers interesting new directions for continuing improvements. Adaptive modifications of the planar transistors offer higher scalability and functionality, higher vertical interconnectivity in between device planes can reduce interconnect delays, higher programmability using configurable elements can provide efficient signal and energy flow, higher digital-analog isolation using ground-planes can provide cross-talk improvements for mixed-signal applications, and a power-aware design can allow control of temperature and power dissipation.