2006 IEEE International Conference on Semiconductor Electronics最新文献_第8页

Pulse Power Failure Model Of Power MOSFET Due To Electrical Overstress Using Tasca Method 基于Tasca法的功率MOSFET超应力脉冲断电模型

2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.380790

N. S. Ismail, I. Ahmad, H. Husain, S. Chuah

引用次数: 4

Device Characteristics of HEMT Structures based on Backgate Contact Method 基于后门接触法的HEMT结构器件特性研究

2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.380733

M. Norman Fadhil Idham, O. Nurul Afzan, H. Soetedjo, A.R. Ahmad Ismat, I. Sabtu, Y. Mohamed Razman, A.M. Abdul Fatah

引用次数: 0

A VLSI Design Framework with Freeware CAD Tools 一个使用免费CAD工具的VLSI设计框架

2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.380768

Y. Teh, F. Mohd-Yasin, M. Reaz, A. Kordesch

引用次数: 0

Studies on Failure Mechanism of ET High Via Resistance in Wafer Fabrication ET高通孔电阻在晶圆制造中的失效机理研究

2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.380765

H. Younan, Tan Sock Khim, Li Kun, Z. Siping

引用次数: 0

High-Performance In0.52Al0.48As/In0.6Ga0.4As Power Metamorphic HEMT for Ka-Band Applications 用于ka波段应用的高性能In0.52Al0.48As/In0.6Ga0.4As功率变质HEMT

2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.381095

Chia-Yuan Chang, E. Chang, Y. Lien, Y. Miyamoto, Szu-Hung Chen, L. Chu

引用次数: 1

Fabrication Study of Solid Microneedles Array Using HNA 利用海航技术制备固体微针阵列的研究

2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.381012

N. A. Aziz, B. Majlis

引用次数: 5

Comparison of the Growth Si-based Crystalline Silicon Carbide (SiC) by Chemical Vapor Deposition (CVD) using Carbon Monoxide (CO) and Treated Carbon Dioxide (CO2) 用一氧化碳(CO)和处理过的二氧化碳(CO2)化学气相沉积(CVD)生长硅基晶体碳化硅(SiC)的比较

2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.381081

A.Y.K. Lim, K. Ibrahim

引用次数: 0

FPGA Implementation of a Canonical Signed Digit Multiplier-less based FFT Processor for Wireless Communication Applications 一种用于无线通信的标准无乘法器FFT处理器的FPGA实现

2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.380712

Mahmud Benhamid, Masuri Othman

{"title":"FPGA Implementation of a Canonical Signed Digit Multiplier-less based FFT Processor for Wireless Communication Applications","authors":"Mahmud Benhamid, Masuri Othman","doi":"10.1109/SMELEC.2006.380712","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380712","url":null,"abstract":"This paper proposes a novel fully parallel FFT architecture based on canonical signed digit (CSD) multiplier-less targeting wireless communication applications, such as IEEE802.15.3a wireless personal area network (WPAN) baseband. The proposed architecture has the advantages of high throughput, less latency, and smaller area. The multiplier-less architecture uses shift- and-add operations to realize the complex multiplier and uses the CSD to optimize these operations. The design has been coded in Verilog HDL targeting Xilinx Virtex-II FPGA series. It is fully implemented and tested on real hardware using Virtex-II FG456 prototype board. Based on this architecture, the implementation of 8-points FFT on Virtex-II can run at a maximum clock frequency of about 400 MHz which lead to about 3.2 GS/s throughput with a latency of 6 clock cycles using 16,580 equivalent gates. Comparison with a conventional parallel architecture design of the same size can run only at a maximum clock frequency of 220 MHz or 1.76 GS/s throughput with a latency of 12 clock cycles using 77,418 equivalent gates for the design. The resulting throughput increases by about 82% while the equivalent gates and latency decrease by about 79% and 50% respectively.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115521594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Aluminum based Two-Port-Clamped-Clamped Resonators 铝基双端口箝位谐振器

2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.381045

M. Al Khusheiny, B. Majlis

引用次数: 5

Queue Time Impact on Defectivity at Post Copper Barrier Seed, Electrochemical Plating, Anneals and Chemical Mechanical Polishing 排队时间对后铜屏障种、电化学镀、退火和化学机械抛光缺陷的影响

2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.380777

Y. A. Wahab, A. Ahmad, Z. Awang

{"title":"Queue Time Impact on Defectivity at Post Copper Barrier Seed, Electrochemical Plating, Anneals and Chemical Mechanical Polishing","authors":"Y. A. Wahab, A. Ahmad, Z. Awang","doi":"10.1109/SMELEC.2006.380777","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380777","url":null,"abstract":"As design rules shrink beyond 0.1.3 mum the development focus has been a gradual shift in the defectivity on copper electroplating integrated circuit manufacturing applications. Effective process inspection and defect identification are key issues for the failure mechanisms in semiconductor manufacturing. In this paper, copper deposition with He in-situ and furnace anneal splits were performed on the Applied Materials SlimCellTM ECP system. The paper outlines the queue time challenges from a defectivity perspective and the solutions implemented that addresses each issue. The analytical techniques used to classify these defects and the methods used to determine their origin is discussed. This paper will attempt to describe the impact of queue time on defectivity challenges and we introduce a new defect characterization scheme that takes the defect generation mechanism and the potential source into account. Further investigation implemented to study the possibility of imposing a time window between seed deposition and plating, plating to anneal duration as well as anneal to CMP in order to posed a significant challenge in differentiating between plating and CMP induced defects. Most defects were observed after chemical-mechanical planarization (CMP) was performed and defects that were generally categorized as missing copper could have resulted from corrosion, from scratches during CMP process from incomplete filling of fine features after plating.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126747453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2