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2006 IEEE International Conference on Semiconductor Electronics最新文献

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Electrical Characteristics of 100 MeV 28Si implantation in GaAs GaAs中100mev 28Si注入的电特性
2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.380779
Y. Ali, A. Narsale, O. Sidek, A. R. Damle, B. Arora
{"title":"Electrical Characteristics of 100 MeV 28Si implantation in GaAs","authors":"Y. Ali, A. Narsale, O. Sidek, A. R. Damle, B. Arora","doi":"10.1109/SMELEC.2006.380779","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380779","url":null,"abstract":"Single crystal n-GaAs substrates have been implanted at room temperature with 100 MeV 28Si ions to a dose of 1times1018 ions/m2. The electrical behaviour of these samples has been investigated after implantation and annealing to 850degC by current voltage (I-V) measurements. The I-V curves show series of complex behaviours with annealing treatments. To understand this complex behaviour, Resistance measurements of these samples using I-V measurements were carried out in the temperature range 100-300 K, which indicate that the as implanted sample and samples annealed to 350degC are dominated by a variable range hoping conduction mechanism, where as for the samples annealed at 450degC and 550degC the electrical conduction is due to hopping between the neighboring defect sites. The electrical transport for the sample annealed at 650degC seems to be dominated by carriers in the extended states. At annealing temperature higher than 650degC, the I-V characteristics are insensitive to measurement temperatures which indicates that the backward diode like structure after 850degC annealing is due to the activation of Si ions and formation of n+ region at the mean ion range and the existence of defect complex p+-type conductivity immediately above that region.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125012444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling of Polyimide MIM Capacitors for Applications in Planar Monolithic Microwave Integrated Circuits 应用于平面单片微波集成电路的聚酰亚胺MIM电容器建模
2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.380796
R. Sanusi, A. Rahim, M. N. Osman, N. Kushairi, A. Rasmi, N. Muhammad, M. Yahya, A. Mat
{"title":"Modeling of Polyimide MIM Capacitors for Applications in Planar Monolithic Microwave Integrated Circuits","authors":"R. Sanusi, A. Rahim, M. N. Osman, N. Kushairi, A. Rasmi, N. Muhammad, M. Yahya, A. Mat","doi":"10.1109/SMELEC.2006.380796","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380796","url":null,"abstract":"Polymide metal-insulator-metal (MIM) overlay capacitors for use in monolithic microwave integrated circuits (MMICs) based on high electron mobility transistors (HEMTs) on gallium arsenide substrates are presented. Modeling of the capacitors was performed using a 2-dimensional electromagnetic CAD simulator to obtain Scattering (S-) parameters for different capacitor dimensions for operating frequencies from 0.05 to 8 GHz. The behaviour of the capacitor as a function of operating frequencies is studied by means of Smith chart. The capacitor is finally represented by a proposed equivalent circuit model to describe its overall behavior for planar MMIC simulations.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115692760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
I/O Process Optimization to Cover Wide Range Operation Voltage 覆盖大范围工作电压的I/O过程优化
2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.380701
D. K. Pal, K. Sabri, M.T.L. Kee, Song Jin Yeong, Park Hyun Suck
{"title":"I/O Process Optimization to Cover Wide Range Operation Voltage","authors":"D. K. Pal, K. Sabri, M.T.L. Kee, Song Jin Yeong, Park Hyun Suck","doi":"10.1109/SMELEC.2006.380701","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380701","url":null,"abstract":"A process has been developed to cover wide range I/O operation voltage (1.8V to 3.3V) without changing the 3.3V I/O library at author's organization to meet the market demand by optimization of 3.3V process. The main emphasis is given on to improve the Idsat current from the baseline and maintain the Ioff comparable as 3.3V process. This process passed all device level reliability test. This process is used to fabricate wide range I/O operation voltage device at author's organization.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123993424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Gas Sensing Potential of Nanocrystalline SnO2 and In2O3 Powders Prepared by Mechanical Milling 机械铣削法制备纳米SnO2和In2O3粉体的气敏电位
2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.381024
G. Wiranto, I. Adiseno, D.P. Hermida, R. Manurung, S. Widodo, M. Siregar
{"title":"The Gas Sensing Potential of Nanocrystalline SnO2 and In2O3 Powders Prepared by Mechanical Milling","authors":"G. Wiranto, I. Adiseno, D.P. Hermida, R. Manurung, S. Widodo, M. Siregar","doi":"10.1109/SMELEC.2006.381024","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381024","url":null,"abstract":"The use of nanocrystalline metal oxide powders to increase the sensitivity of gas sensors has been the subject of this research. Of particular interest to our application in environmental monitoring is ln<sub>2</sub>O<sub>3</sub> and SnO<sub>2</sub>, which are known, respectively, to have a high sensitivity to oxidising pollutant gases such as NO<sub>2</sub> and 03, and reducing pollutant gases such as CO and NH<sub>3</sub>. Preparation of undoped nanocrystalline SnO<sub>2</sub> and ln<sub>2</sub>O<sub>3</sub> powders by mechanical milling via centrifugal action have been conducted. The technique used has allowed the reduction of grain sizes from 3-5 mum to below 100 nm with no contaminating carbon content, as confirmed by SEM and EDS spectra analysis. Furthermore, the FTIR spectra indicated that the SnO<sub>2</sub> nanopowders had a strong band at 671 cm<sup>-1</sup> and ln<sub>2</sub>O<sub>3</sub> at 601 cm<sup>-1</sup>. The resulting nanopowders were then mixed with alpha-based terpinol to produce a thick film paste as an active material of gas sensors, and applied to an alumina platform consisting of AgPt heater and electrode tracks.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130318557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Circuit Debug using Time Resolved Emission (TRE) Prober - A Case Study 使用时间分辨发射(TRE)探测器进行电路调试-一个案例研究
2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.380711
Houn Wai Wong, P.F. Low, V.K. Wong
{"title":"Circuit Debug using Time Resolved Emission (TRE) Prober - A Case Study","authors":"Houn Wai Wong, P.F. Low, V.K. Wong","doi":"10.1109/SMELEC.2006.380711","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380711","url":null,"abstract":"Time resolved emission microscopy (TRE) is a revolutionary tool used in advanced microprocessors silicon debug. Unlike other debug tools, the interpretation of TRE data may not be straightforward and can sometimes be misleading. In this paper we show through a case study why this is true. Interpretation of TRE data should be done carefully with good knowledge on device emission physics, circuit behavior and creative fault analysis.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131085298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Failure Analysis Approach in Memory Failure of SOI Devices SOI器件内存失效的失效分析方法
2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.380723
S. P. Neo, S. K. Loh, Z.G. Song, S.P. Zhao
{"title":"Failure Analysis Approach in Memory Failure of SOI Devices","authors":"S. P. Neo, S. K. Loh, Z.G. Song, S.P. Zhao","doi":"10.1109/SMELEC.2006.380723","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380723","url":null,"abstract":"Silicon-on-insulator (SOI) is a sandwich structure consisting of a thin insulating layer, such as silicon dioxide or glass sandwiching between a thin layer of silicon (T-Si) and the silicon substrate. The incorporation of the insulating layer between the T-Si and the silicon substrate has greatly changed the front-end process of microelectronic devices and thus the approach of failure analysis would be different compared to that of bulk technology. In this paper, approaches to analyze the single bit failure and pair bit failure in memory failure of SOI wafers would be presented.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129315645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of Rapid Thermal Annealing (RTA) on n-Contact of 980 nm Oxide VCSEL 快速热退火(RTA)对980 nm氧化物VCSEL n-接触的影响
2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.381084
M.S.K. Anuar, A. M. Sharizal, S. Mitani, Y. M. Razman, A. Mat, P. Choudhury
{"title":"Effect of Rapid Thermal Annealing (RTA) on n-Contact of 980 nm Oxide VCSEL","authors":"M.S.K. Anuar, A. M. Sharizal, S. Mitani, Y. M. Razman, A. Mat, P. Choudhury","doi":"10.1109/SMELEC.2006.381084","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381084","url":null,"abstract":"The paper deals with the development of Ni/Au/Ge/Au ohmic contacts for the fabrication of VCSELs to be operated in the 980 nm of the electromagnetic (EM) spectrum. The VCSEL structures are grown by the process of molecular beam epitaxy (MBE) whereas the contacts are deposited by electron beam evaporator. The n-contact metallization has been performed along with RTA before as well as after the fabrication of the VCSEL structure, and the effect of RTA treatment on the grown VCSEL has been studied in the different cases.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128735735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Performance of OCDMA Systems Using AND Subtraction Technique 使用和减法技术的OCDMA系统性能
2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.381104
S. Aljunid, F. Hasson, M.D.A. Samad, M. Abdullah, M. Othman, S. Shaari
{"title":"Performance of OCDMA Systems Using AND Subtraction Technique","authors":"S. Aljunid, F. Hasson, M.D.A. Samad, M. Abdullah, M. Othman, S. Shaari","doi":"10.1109/SMELEC.2006.381104","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381104","url":null,"abstract":"A new detection scheme, namely AND subtraction technique is proposed and presented in this paper. The theory is being elaborated and experimental results have been done by comparing double-weight (DW) code against the existing code, Hadamard. In this paper we have proved that AND subtraction technique gives better bit error rates (BER) performance than Complementary subtraction technique against the received power level.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126318688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
SIMS Analysis of Gate Oxide Breakdown Due to Tungsten Contamination 钨污染栅极氧化物击穿的SIMS分析
2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.381107
D. Gui, Z. X. Xing, Z. Mo, Y. Hua, S.P. Zhao
{"title":"SIMS Analysis of Gate Oxide Breakdown Due to Tungsten Contamination","authors":"D. Gui, Z. X. Xing, Z. Mo, Y. Hua, S.P. Zhao","doi":"10.1109/SMELEC.2006.381107","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381107","url":null,"abstract":"The gate oxide is the most fragile element of metal-oxide-semiconductor (MOS) transistor. Metallic contamination in the gate oxide leads to high leak current and even gate oxide breakdown. In this paper, we have investigated a failure case of NMOS gate oxide breakdown using secondary ion mass spectrometry (SIMS) because of its excellent sensitivity. The SIMS depth profiles at the test pad in the scribe line showed that the gate oxide breakdown was caused by tungsten (W) contamination. Further study indicated that W contaminated wafers during n-poly implantation by the re-deposition from the supporting disk of implanter. Based on the SIMS results, measures have been suggested to reduce the W contamination.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114564779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Front End Defects on Deep Submicron Devices 深亚微米器件的前端缺陷
2006 IEEE International Conference on Semiconductor Electronics Pub Date : 2006-11-01 DOI: 10.1109/SMELEC.2006.380724
S. P. Neo, S. K. Loh, Z.G. Song, S.P. Zhao
{"title":"Front End Defects on Deep Submicron Devices","authors":"S. P. Neo, S. K. Loh, Z.G. Song, S.P. Zhao","doi":"10.1109/SMELEC.2006.380724","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380724","url":null,"abstract":"Front end defects are usually more intricate as compared to back end defects, and as technology scale down into deep submicron regime, failure analysis of the front end defect is becoming even more challenging due to the increase in complexity of the process. In this paper, failure analysis on three types of front- end defect has been discussed. These defects are cobalt silicide at poly sidewall causing active to poly bridging, amorphous layer under contact and broken silicide on poly line, which were observed on 90 nm SOI wafers.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114518859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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