Failure Analysis Approach in Memory Failure of SOI Devices

Abstract

Silicon-on-insulator (SOI) is a sandwich structure consisting of a thin insulating layer, such as silicon dioxide or glass sandwiching between a thin layer of silicon (T-Si) and the silicon substrate. The incorporation of the insulating layer between the T-Si and the silicon substrate has greatly changed the front-end process of microelectronic devices and thus the approach of failure analysis would be different compared to that of bulk technology. In this paper, approaches to analyze the single bit failure and pair bit failure in memory failure of SOI wafers would be presented.