2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献_第7页

Current sensing completion detection in dual-rail asynchronous systems 双轨异步系统的电流传感完井检测

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219021

L. Nagy, V. Stopjaková

引用次数: 3

VARMA—VARiability modelling and analysis tool varma变异性建模和分析工具

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219091

G. Russell, F. Burns, A. Yakovlev

引用次数: 4

NAND/NOR gate polymorphism in low temperature environment 低温环境下NAND/NOR门多态性研究

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219020

R. Ruzicka, Václav Simek

{"title":"NAND/NOR gate polymorphism in low temperature environment","authors":"R. Ruzicka, Václav Simek","doi":"10.1109/DDECS.2012.6219020","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219020","url":null,"abstract":"The fundamental aspect behind this paper is focused on behaviour of polymorphic digital circuits in potentially harsh operating environment. The area of polymorphic electronics takes and an advantage of inherently built-in features that open up the possibility for on-the-fly adjustment of a particular circuit function with respect to the environment. The most prevalent benefit here is connected with the fact that space-efficient circuit implementation can be achieved due to the adoption of polymorphic principles and, thus, eliminate the need for an additional function change controller. The experimental setup was based around reconfigurable polymorphic chip REPOMO32, which is primarily designed to be configured (in addition to the configuration bit stream) by means of using the level of power supply voltage (Vdd), and carrier board with all necessary capabilities for temperature measurement up to -40C boundary and its response analysis. Experiments clearly indicate that polymorphic gates in the chip can be easily controlled not only by Vdd, but also by temperature. The obtained results also prove that the physical design of the REPOMO32 chip is robust enough under wide range f operating temperature.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122117207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Improving the iterative power of resynthesis 提高再合成的迭代能力

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219019

P. Fiser, Jan Schmidt

引用次数: 9

Reconfigurable time interval measurement circuit incorporating a programmable gain time difference amplifier 包含可编程增益时间差放大器的可重构时间间隔测量电路

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219089

A. Alahmadi, G. Russell, A. Yakovlev

引用次数: 12

Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST 基于并行混合BIST的多时钟域soc功耗约束测试

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219022

M. Haghbayan, S. Safari, Z. Navabi

引用次数: 10

A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage sensing technique 采用分位线和新型两级传感技术的65nm CMOS 512 kb SRAM

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219052

Xiang Zheng, Ming Liu, Hong Chen, Huamin Cao, Cong Wang, Zhiqiang Gao

引用次数: 1

Efficient digital design for automotive mixed-signal ASICs using simulink 利用simulink实现汽车混合信号专用集成电路的高效数字化设计

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219090

Andreas Mauderer, M. Freier, Jan-Hendrik Oetjens, W. Rosenstiel

引用次数: 3

Application of IDDT test towards increasing SRAM reliability in nanometer technologies IDDT测试在纳米技术中提高SRAM可靠性的应用

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219046

G. Gyepes, D. Arbet, J. Brenkus, V. Stopjaková

引用次数: 11

Effective RT-level software-based self-testing of embedded processor cores 有效的基于rt级软件的嵌入式处理器内核自检

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219059

P. Kabiri, Z. Navabi

{"title":"Effective RT-level software-based self-testing of embedded processor cores","authors":"P. Kabiri, Z. Navabi","doi":"10.1109/DDECS.2012.6219059","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219059","url":null,"abstract":"Embedded processors are often used in systems that are both safety-critical and long-living. Therefore testing of these devices is critical not only after production, but also in the field. Due to the limited accessibility of embedded processors, testing of such systems is a major challenge in terms of ultra-deep submicron issues. Scan based testing methods cannot be applied to embedded processor cores which cannot be modified to meet the design requirements for scan insertion. From the other side, generating test vectors for these high gate count devices is a major task. This paper presents a high level, component-oriented software-based self-testing method which achieves a high stuck-at-fault coverage for an embedded processor core. The method requires no DFT or changing the processor architecture. The proposed method is high level in the sense that it is based on the knowledge of the Instruction Set Architecture (ISA) and Register Transfer Level (RTL) description of the processor. The method is well suited for meeting the challenges of testing SoCs which contain embedded processor cores. Our methodology is superior in terms of test quality in such a way that significantly increases fault coverage and reduces test time. The proposed method outperforms all existing method in terms of fault coverage.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122379295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11