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2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献

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The architecture and the technology characterization of an FPGA-based customizable Application-Specific Vector Processor 基于fpga的可定制专用矢量处理器的体系结构和技术表征
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219026
J. Sykora, L. Kohout, R. Bartosinski, Leos Kafka, M. Danek, P. Honzík
{"title":"The architecture and the technology characterization of an FPGA-based customizable Application-Specific Vector Processor","authors":"J. Sykora, L. Kohout, R. Bartosinski, Leos Kafka, M. Danek, P. Honzík","doi":"10.1109/DDECS.2012.6219026","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219026","url":null,"abstract":"The traditional approach to IP core design is to use simulations with test vectors. This is not feasible when dealing with complex function cores such as the Image Segmentation case-study algorithm in this paper. An algorithm developer needs to carry out experiments on large real-world data sets, with fast turn-around times, and in real time to facilitate performance tuning and incremental development. We propose a methodology called Application-Specific Vector Processor (ASVP). The ASVP approach first constructs a programmable architecture customized for a given application, then employs software techniques to develop firmware that implements the algorithm. Our sample implementation that supports the Image Segmentation kernel is capable of 332 MFLOPs, 400 MFLOPs, and 250 MFLOPs per coprocessor core in Virtex 5, Virtex 6 and Spartan 6 technologies, respectively. The core size is roughly 1500 slices, depending on the configuration and technology.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116884669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A new SAT-based ATPG for generating highly compacted test sets 一个新的基于sat的ATPG，用于生成高度压缩的测试集
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219063
Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, F. Hapke, R. Drechsler
{"title":"A new SAT-based ATPG for generating highly compacted test sets","authors":"Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, F. Hapke, R. Drechsler","doi":"10.1109/DDECS.2012.6219063","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219063","url":null,"abstract":"The test set size is a highly important factor in the post-production test of circuits. A high pattern count in the test set leads to long test application time and exorbitant test costs. We propose a new test generation approach which has the ability to reduce the test set size significantly. In contrast to previous SAT-based ATPG techniques which were focused on dealing with hard single faults, the proposed approach employs the robustness of SAT-solvers to primarily push test compaction. Furthermore, a concept is introduced how the novel technique can be flexibly integrated into an existing industrial flow to reduce the pattern count. Experimental results on large industrial circuits show that the approach is able to reduce the pattern count of up to 63% compared to state-of-the-art dynamic compaction techniques.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128226838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
An evaluation of the application dependent FPGA test method 一种评估应用的FPGA测试方法
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219017
M. Rozkovec, Jiri Jenícek, O. Novák
{"title":"An evaluation of the application dependent FPGA test method","authors":"M. Rozkovec, Jiri Jenícek, O. Novák","doi":"10.1109/DDECS.2012.6219017","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219017","url":null,"abstract":"In this paper we evaluate the application dependent FPGA (Field Programmable Gate Array) test method which uses an ASIC BIST (Application Specific Integrated Circuit Built-in Self-Test) techniques and tools and efficiently utilizes the properties of nowadays FPGA devices, such as the partial runtime reconfiguration. The method splits the tested circuit and then uses partial reconfiguration to change the role of the partitioned modules, which may act as testers or as response analyzers. Circuit partitions are translated to an ATPG (Automatic Test Pattern Generator) readable format and the deterministic test vectors are generated. The compression tool is used to compress test patterns, thus it is not required to create additional test access interfaces or to use multiple reconfigurations. We show that the usage of the method reduces test time and memory requirements and it leads to good test coverage results. Each step of the design flow is described and evaluated in detail as well as the experimental results and the hardware.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134466257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Low-area boundary BIST architecture for mesh-like network-on-chip 面向类网格片上网络的低面积边界BIST结构
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219032
J. Raik, V. Govind
{"title":"Low-area boundary BIST architecture for mesh-like network-on-chip","authors":"J. Raik, V. Govind","doi":"10.1109/DDECS.2012.6219032","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219032","url":null,"abstract":"Current paper proposes a Built-In Self-Test (BIST) architecture for targeting the routing infrastructure of mesh-like NoCs from their boundaries. The architecture contains a counter and a Finite State Machine (FSM) implementing the test configurations. Test data is generated and test responses compacted by a dedicated hardware structure requiring very little silicon area. The advantages of this new boundary BIST concept with respect to existing methods is that costly data wrappers in the NoC network are unnecessary, and thus, area and performance penalties are avoided. We have also improved previously developed test configurations. Experiments show that up to two orders of magnitude gains in the speed of testing are achieved using the new method for large NoCs.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129690674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Security properties of oscillator rings in true random number generators 真随机数发生器中振环的安全性
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219041
Knut Wold, Slobodan V. Petrovic
{"title":"Security properties of oscillator rings in true random number generators","authors":"Knut Wold, Slobodan V. Petrovic","doi":"10.1109/DDECS.2012.6219041","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219041","url":null,"abstract":"In order to achieve high security in a true random number generator (TRNG) consisting of several equal length oscillator rings implemented in a field programmable gate array (FPGA), it is important that the rings do not oscillate with identical frequencies and phases. In such a degenerate case, the entropy of the TRNG output bit sequence would be drastically reduced. In this paper, an investigation of the properties regarding interaction between the oscillator rings, the dispersion in the ring frequencies and correlation and dependencies between oscillator rings is carried out in three different FPGA device families. The experiments show that there are interactions and correlation between oscillator rings, and these effects need to be compensated in order to improve the security of such a TRNG design.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130281266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Optimised Power Supply Unit Design 优化电源单元设计
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219054
M. Pospisilik, M. Adamek
{"title":"Optimised Power Supply Unit Design","authors":"M. Pospisilik, M. Adamek","doi":"10.1109/DDECS.2012.6219054","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219054","url":null,"abstract":"At Tomas Bata University a Ph.D. project focused on Autonomous monitoring system is being solved, dealing with an independent operation of a small airship inside an enclosed hall. It includes a design of the controlling unit, including the power delivery. The power source must be equipped with three voltage converters (SMPS) capable of delivering standardized voltages to the particular circuits of the controlling unit. As the energy source, two-cell Li-Pol accumulator is employed. In this paper an approach to the design of the synchronized voltage converters set is described, considering the following requirements: preserving a long life of the Li-Pol accumulator, high supply voltage conversion efficiency, overcurrent protection, easy hibernation and the last but not least, low disturbing electromagnetic radiation. The main part is dedicated to the optimized synchronization of the particular SMPSs in order the minimum pulse component of the supply current was achieved.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133144300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A user-level library for fault tolerance on shared memory multicore systems 一个用于共享内存多核系统容错的用户级库
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219071
Hamid Mushtaq, Z. Al-Ars, K. Bertels
{"title":"A user-level library for fault tolerance on shared memory multicore systems","authors":"Hamid Mushtaq, Z. Al-Ars, K. Bertels","doi":"10.1109/DDECS.2012.6219071","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219071","url":null,"abstract":"The ever decreasing transistor size has made it possible to integrate multiple cores on a single die. On the downside, this has introduced reliability concerns as smaller transistors are more prone to both transient and permanent faults. However, the abundant extra processing resources of a multicore system can be exploited to provide fault tolerance by using redundant execution. We have designed a library for multicore processing, that can make a multithreaded user-level application fault tolerant by simple modifications to the code. It uses the abundant cores found in the system to perform redundant execution for error detection. Besides that, it also allows recovery through checkpoint/rollback. Our library is portable since it does not depend on any special hardware. Furthermore, the overhead (up to 46% for 4 threads), our library adds to the original application, is less than other existing approaches, such as Respec.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123233956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit 基于现场延迟监测的图像处理电路自适应电压缩放
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219058
M. Wirnshofer, L. Heiß, Anil Narayan Kakade, N. P. Aryan, G. Georgakos, D. Schmitt-Landsiedel
{"title":"Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit","authors":"M. Wirnshofer, L. Heiß, Anil Narayan Kakade, N. P. Aryan, G. Georgakos, D. Schmitt-Landsiedel","doi":"10.1109/DDECS.2012.6219058","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219058","url":null,"abstract":"The proposed voltage scheme adaptively tunes the supply voltage of digital circuits, according to PVTA variations. By exploiting unused timing margin, produced by state-of-the-art worst-case designs, energy efficiency is significantly increased. In-situ delay monitoring is performed by enhanced flip-flops, observing signal delays in critical paths. We introduce a novel methodology to analyze the closed-loop behavior of the overall control scheme by a Markov approach, based on extensive transistor simulations. The digital logic and the AVS control circuitry are designed in 65nm CMOS for an image processing application. The AVS approach optimizes dynamic and leakage power dependent on the user-defined image quality requirements.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121940633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Low power balun Design for 1.575 GHz in 90 nm CMOS rechnology 基于90纳米CMOS技术的1.575 GHz低功耗均衡器设计
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219067
Jacek Gradzki
{"title":"Low power balun Design for 1.575 GHz in 90 nm CMOS rechnology","authors":"Jacek Gradzki","doi":"10.1109/DDECS.2012.6219067","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219067","url":null,"abstract":"In this paper low power balun design is presented. It is optimized for 1.575 GHz and designed in 90 nm UMC CMOS technology. Current consumption is only 0.44 mA under 1.2 V supply voltage. The simulation shows that gain and phase imbalance are equal to 0.08 dB and 0.045°, respectively. Single-ended power gain of this circuit is 2.2 dB. A special dimension matching has been made to minimize circuit susceptibility to variation of the manufacturing process.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127113175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VHDLVisualizer: HDL model visualization with simulation-based verification VHDLVisualizer: HDL模型可视化与基于仿真的验证
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219056
Dominik Macko, K. Jelemenská
{"title":"VHDLVisualizer: HDL model visualization with simulation-based verification","authors":"Dominik Macko, K. Jelemenská","doi":"10.1109/DDECS.2012.6219056","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219056","url":null,"abstract":"The usage of the HDLs (Hardware Description Languages) in the present digital system development process is indispensable. Although, their great contribution is undeniable, they also bring about several disadvantages. The textual form of an HDL model is less illustrative for a human being than schematic representation of its structure. Moreover, simulation of such models is most commonly displayed in a waveform representation, even though sufficient for verification, it is hard-to-identify design errors. The paper presents a tool for supporting both, the model structure visualization and the simulation results in the visualized structure display.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"34 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116591441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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