2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献_第5页

Radiation-tolerant combinational gates - an implementation based comparison 耐辐射组合门——一种基于比较的实现

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219036

Varadan Savulimedu Veeravalli, A. Steininger

引用次数: 5

Synthesis of Petri nets into FPGA with operation flexible memories

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219016

A. Bukowiec, M. Adamski

引用次数: 16

A new analog output buffer for data driver of active matrix displays using low-temperature polycrystalline silicon thin-film transistors 基于低温多晶硅薄膜晶体管的有源矩阵显示数据驱动模拟输出缓冲器

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219075

I. Pappas, S. Siskos, A. Hatzopoulos

引用次数: 0

A three-dimensional DRAM using floating body cell in FDSOI devices FDSOI器件中采用浮体单元的三维DRAM

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219044

Xuelian Liu, A. Zia, M. R. LeRoy, S. Raman, R. Clarke, R. Kraft, J. McDonald

引用次数: 2

On the use of assertions for embedded-software dynamic verification 论断言在嵌入式软件动态验证中的应用

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219083

G. D. Guglielmo, L. D. Guglielmo, F. Fummi, G. Pravadelli

{"title":"On the use of assertions for embedded-software dynamic verification","authors":"G. D. Guglielmo, L. D. Guglielmo, F. Fummi, G. Pravadelli","doi":"10.1109/DDECS.2012.6219083","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219083","url":null,"abstract":"Assertion-based verification (ABV) affirmed as an effective methodology for functional verification, i.e., design specification conformance, of embedded systems. Academia and industry have throughly investigated formal ABV for high-budget or safety-critical hardware and software projects, while the scalability of dynamic ABV has led to the introduction of standard languages and commercial tools addressing hardware design verification, emulation, and silicon debug. However, up to now, there were only limited studies concerning the application of dynamic ABV to embedded-software design and verification flow. We propose an analysis aiming to bridge such a gap. In particular, we illustrate how dynamic ABV can integrate and improve the various stages of the embedded-software verification flow. The analysis leads us to develop a comprehensive ABV environment that integrates the still missing automatic synthesis of executable checkers for embedded software. Experiments show that the proposed environment reduces the verification-team efforts and makes dynamic ABV practical for embedded-software design.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114537589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Monitoring-driven HW/SW interrupt overload prevention for embedded real-time systems 嵌入式实时系统监控驱动的硬件/软件中断过载预防

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219037

Josef Strnadel

引用次数: 8

A SBST strategy to test microprocessors' Branch Target Buffer 一种测试微处理器分支目标缓冲区的SBST策略

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219079

P. Bernardi, Lyl M. Ciganda Brasca, M. Grosso, E. Sánchez, M. Reorda

引用次数: 11

Complementary edge alignment and digital output signal speed-up CMOS positive feedback latches 互补边缘对准和数字输出信号加速CMOS正反馈锁存器

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219088

V. Milovanovic, H. Zimmermann

引用次数: 2

On-chip aging sensor to monitor NBTI effect in nano-scale SRAM 片上老化传感器监测纳米SRAM中NBTI效应

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219087

A. Ceratti, T. Copetti, L. Bolzani, F. Vargas

{"title":"On-chip aging sensor to monitor NBTI effect in nano-scale SRAM","authors":"A. Ceratti, T. Copetti, L. Bolzani, F. Vargas","doi":"10.1109/DDECS.2012.6219087","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219087","url":null,"abstract":"Today, the increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of a System-on-Chip (SoC). Therefore, SRAM's robustness is considered crucial in order to guarantee the reliability of such SoCs over lifetime. In this context, one of the most important phenomena that degrades Nano-scale SRAMs reliability is related to Negative-Bias Temperature Instability (NBTI), which accelerates memory cells aging. This paper proposes a new approach to detect SRAM aging during system lifetime based on an On-Chip Aging Sensor (OCAS). The OCAS is able to detect any specific aging state of a cell in the SRAM array. The strategy is based on the connection of one OCAS every SRAM column, each periodically performing off-line tests by monitoring the write operations on the SRAM cells in order to detect aging. To prevent the OCAS from aging and from dissipating leakage power, the OCAS circuitry is powered-off during its idle periods. Experimental results demonstrate the sensor's high sensitivity to detect early aging states and therefore, guaranteeing high memory reliability. Finally, the area overhead related to the sensors' insertion is almost negligible.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123224249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Selective redundancy to improve reliability and to slow down delay degradation due to gate oxide breakdown 选择性冗余，以提高可靠性和减缓延迟退化，由于栅极氧化物击穿

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219015

Hagen Sämrow, C. Cornelius, Philipp Gorski, Andreas Tockhorn, D. Timmermann

{"title":"Selective redundancy to improve reliability and to slow down delay degradation due to gate oxide breakdown","authors":"Hagen Sämrow, C. Cornelius, Philipp Gorski, Andreas Tockhorn, D. Timmermann","doi":"10.1109/DDECS.2012.6219015","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219015","url":null,"abstract":"Because of the aggressive scaling into the nanometer regime, degradation due to wearout significantly impairs design parameters. For instance, such wearout is caused by gate oxide breakdown, which decreases the operating lifetime of integrated circuits to an extent that cannot be neglected by circuit designers to date. In this paper, we introduce an approach which applies selective redundancy to different combinational designs in order to improve reliability as regards gate oxide breakdown. Therefore, the most vulnerable transistor stacks of standard cells are doubled based on activity and the propagation delay of the design. Finally, reliability improvements of up to 75% are presented that are gained with Spice simulations. Such improvements come at the price of overhead for area and power consumption as well as delay of at most 14%. However, it is interesting to notice that the initial delay penalty of our enhanced designs finally turn into a timing advantage, as the designs are more and more affected by wearout over time. Hence, this advantage translates into further reliability improvements when clock requirements are also considered. Besides, it needs to be noted that the presented strategies can additionally improve defect yield.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124895810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1