Radiation-tolerant combinational gates - an implementation based comparison

As newer CMOS technologies are known to be more susceptible to particle hits, radiation tolerance is receiving increased attention. Several techniques for attaining this property are available in the literature already. However, virtually all of the publications refer to an inverter circuit, and the related robustness assessments (if any) are hard to compare, since important characteristics, such as technology or fault model, differ. In this paper we fill this gap by applying the available concepts to combinational gates, in particular an XOR gate, using the same concrete technology and sizing as well as the same fault model. By means of extensive analog simulations we verify and finally tune their robustness to the same level. On this foundation we can then make a comparison of the respective overheads and problems, such that it becomes relatively easy to distinguish efficient solutions from problematic ones.