2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献

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Temperature and on-chip crosstalk measurement using ring oscillators in FPGA 在FPGA中使用环形振荡器测量温度和片上串扰
Martin Gag, Tim Wegner, Ansgar Waschki, D. Timmermann
{"title":"Temperature and on-chip crosstalk measurement using ring oscillators in FPGA","authors":"Martin Gag, Tim Wegner, Ansgar Waschki, D. Timmermann","doi":"10.1109/DDECS.2012.6219057","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219057","url":null,"abstract":"Temperature management and signal integrity are two highly relevant challenges for nano scale CMOS devices. As temperature of integrated circuits affects the frequency of defect mechanisms' occurrence and consequently influences reliability, temperature monitoring is inevitable. To provide the necessary thermal sensors, different techniques are available. One is to use the temperature dependent speed of logic devices and perform a time to digital conversion. In this work, this approach is evaluated for the use in FPGAs. Furthermore, problems regarding signal integrity affect the reliability of highly integrated circuits. Therefore, we discuss the possibilities of crosstalk effects in FPGA and demonstrate a method for time to digital conversion in order to measure the impact of coupling capacitances in the interconnection structure of FPGAs. The main contribution of the introduced method is to enable simple post-production investigations for signal integrity of programmable devices.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121244424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Genetic method for compressed skewed-load delay test generation 压缩偏载延迟试验生成的遗传方法
R. Dobai, M. Baláz
{"title":"Genetic method for compressed skewed-load delay test generation","authors":"R. Dobai, M. Baláz","doi":"10.1109/DDECS.2012.6219065","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219065","url":null,"abstract":"Complex system-on-chips (SOCs) require low-overhead testability methods to keep the test cost at an acceptable level. Skewed-load tests seem to be the appropriate way to test delay faults in these SOCs because the test application requires only one storage element per scan cell. Compressed skewed-load test generator based on genetic algorithm is proposed for wrapper-based logic cores of SOCs. Deterministic population-initialization is used to ensure the highest achievable transition delay fault coverage for the given wrapper and scan cell order. The developed genetic algorithm performs test data compression by generating test vectors containing already overlapped test vector pairs. The experimental results show high fault coverages, decreased test lengths and better scalability in comparison to recent methods.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"416 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123574856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Lightweight benchmarking of platforms for network traffic processing 网络流量处理平台的轻量级基准测试
Pavol Korcek, M. Zádník
{"title":"Lightweight benchmarking of platforms for network traffic processing","authors":"Pavol Korcek, M. Zádník","doi":"10.1109/DDECS.2012.6219074","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219074","url":null,"abstract":"Embedded processors seem to be a viable solution for network traffic processing. We can observe that the current network development boards utilize ARM, MIPS rather than specialized network processors. The processors for embedded applications are low cost, low power but their performance is not clear. In this work we aim at revealing their performance in terms of their throughput and processing power. To this end, we select three network processing functions such as longest prefix match, filtering and pattern matching. We benchmark several available platforms with embedded processors by implementing and running these tests in a controlled environment.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124961342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Digital-driven formal analog verification for asynchronously feed-backed circuitries 异步反馈电路的数字驱动形式模拟验证
G. Uygur, S. Sattler
{"title":"Digital-driven formal analog verification for asynchronously feed-backed circuitries","authors":"G. Uygur, S. Sattler","doi":"10.1109/DDECS.2012.6219068","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219068","url":null,"abstract":"In this paper we show a road map for successively dividing an asynchronously feed-backed circuitry into its substructures, and provide several intuitive and formal approaches to recompose structural behavior from its substructures. Each dividing granularity and composition provides specific information about safety, stability, reliability and reproducibility. We further classify and discuss behavioral model and stability criteria on bases of the given structural properties and present a use-case. Implementation results are given and discussed formally with respect to extracted structure-weaknesses and safety aspects. The method exhibits analog properties of the structure like multivalued information flow, propagation time and superpositions that can lead to information corruptness.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126693863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
HLS-DoNoC: High-level simulator for dynamically organizational NoCs HLS-DoNoC:用于动态组织noc的高级模拟器
L. Guang, E. Nigussie, J. Plosila, J. Isoaho, H. Tenhunen
{"title":"HLS-DoNoC: High-level simulator for dynamically organizational NoCs","authors":"L. Guang, E. Nigussie, J. Plosila, J. Isoaho, H. Tenhunen","doi":"10.1109/DDECS.2012.6219031","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219031","url":null,"abstract":"A high-level simulator is presented for the design and analysis of dynamically organizational Networks-on-Chip (DoNoCs). The DoNoC is able to organize statically or dynamically different network nodes for run-time coarse and fine grained reconfiguration, in particular power management. As an important step in the design flow, a simulator for early-stage design exploration is the focus of the paper. Built upon classic wormhole-based NoC architecture, the simulator is capable of experimenting diverse run-time monitoring and reconfiguration methods. In particular, dynamic clusterization can be performed with inter-cluster interfaces properly configured at the run-time. The simulator is flit-level accurate, trace-driven, and easy-to-reconfigure. It supports both synchronous and ratiochronous timing, and can provide the communication performance and power/energy consumption. The paper demonstrates the usage of the simulator in the design of various cluster-based power management schemes.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115799177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Test platform for fault tolerant systems design properties verification 测试平台的容错系统设计特性验证
M. Straka, Lukas Miculka, Jan Kastil, Z. Kotásek
{"title":"Test platform for fault tolerant systems design properties verification","authors":"M. Straka, Lukas Miculka, Jan Kastil, Z. Kotásek","doi":"10.1109/DDECS.2012.6219084","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219084","url":null,"abstract":"In this paper, a methodology for fault tolerant systems design properties verification is presented together with recovery technique for a fault tolerant system after soft errors occurrence in a SRAM-based FPGA. First, the principles of test platform based on an external SEU injector are presented; all components of test platform and their role during SEU simulation are described. Then, a recovery technique based on the generic partial dynamic reconfiguration controller implemented inside an FPGA is presented. The controller is used for the identification of a faulty module in the fault tolerant system, reconfiguration of this module through ICAP interface and synchronization of the module after reconfiguration process with other modules in the system. The controller can be used for the identification of permanent faults in the FPGA structure as well. The first experiments with a test platform and reconfiguration controller are discussed in this paper.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134453554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Developing a new phase noise estimation technique based on time varying model 提出了一种基于时变模型的相位噪声估计方法
S. I. Tous, E. Mohamadi, M. Mousavi, R. Abadi, E. Kargaran, H. Nabovati
{"title":"Developing a new phase noise estimation technique based on time varying model","authors":"S. I. Tous, E. Mohamadi, M. Mousavi, R. Abadi, E. Kargaran, H. Nabovati","doi":"10.1109/DDECS.2012.6219073","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219073","url":null,"abstract":"Since all oscillators are periodically time varying systems, to accurate phase noise calculation and simulation, time varying model should be considered. Linear time invariant and linear time variant models for calculating phase noise are studied in this paper. Moreover a simple method for Impulse Sensitivity Function (ISF) calculation is proposed. This method promises more effective and simpler than previous methods which are published in the literature. The proposed method validity has been confirmed by simulation.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128281538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1V, low power, high-gain, 3 – 11 GHz double-balanced CMOS sub-harmonic mixer 一个1V,低功率,高增益,3 - 11ghz双平衡CMOS次谐波混频器
Rouhollah Feghhi, S. Naseh
{"title":"A 1V, low power, high-gain, 3 – 11 GHz double-balanced CMOS sub-harmonic mixer","authors":"Rouhollah Feghhi, S. Naseh","doi":"10.1109/ICICDT.2012.6232866","DOIUrl":"https://doi.org/10.1109/ICICDT.2012.6232866","url":null,"abstract":"Design and simulation of a low power ultra wide band doubly balanced 2× sub-harmonic direct conversion mixer in a 0.18-μm CMOS technology is presented. The basic idea of the proposed mixer is adopted from the conventional Gilbert cell mixer, with two modifications incorporated. The first is that each of the switching quad transistors is replaced with a pair of transistors where their two drains, and also their two sources, are connected together (forming a “switching octet” instead of a “switching quad”). The signals driving the switching octet now has 4 different phases 0°, 90°, 180° and 270° (as opposed to the 2 phases 0° and 180° needed for the conventional Gilbert cell) which their waveform is in such a way that none of the octet transistors driven by different phases will be simultaneously on. These 4 driving phases are generated by a circuit block comprised of an 8-phase oscillator and 4 frequency doublers. The second modification is that each of the two transconductance transistors is replaced with an inductor. In the proposed mixer the RF signal is applied to the sources of the switching octet transistors. Because of this modification, stacking of transistors is avoided, allowing low voltage operation of the circuit. Simulation results performed using Hspice show The mixer draws 4.5 mA of dc current from a 1 V power supply, and achieves a bandwidth from 3 GHz to 11 GHz, a voltage conversion gain (CG) of 14~23dB, and 3rd intermodulation intercept points (IIP3) of -1.2 dBm.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121465676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Lightweight cipher resistivity against brute-force attack: Analysis of PRESENT 抗暴力攻击的轻量级密码电阻率:PRESENT分析
J. Pospíšil, M. Novotný
{"title":"Lightweight cipher resistivity against brute-force attack: Analysis of PRESENT","authors":"J. Pospíšil, M. Novotný","doi":"10.1109/DDECS.2012.6219055","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219055","url":null,"abstract":"The PRESENT cipher is symmetric block cipher with 64 bits of data block and 80 (or 128) bits of key. It is based on Substitution-permutation network and consists of 31 rounds. PRESENT is intended to be implemented in small embedded and contactless systems, thus its design needs only small amount of chip area and consumes low power. In this work we evaluate the resistance of PRESENT against brute-force attack. We determine the computational demand of this type of attack conducted on special parallel hardware COPACOBANA consisting of array of FPGA chips with custom design.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134280150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
D&T Presenter - electronic interactive system for design and test education D&T演示-设计和测试教育的电子交互系统
Matej Hlatký, Valter Martinek, E. Gramatová
{"title":"D&T Presenter - electronic interactive system for design and test education","authors":"Matej Hlatký, Valter Martinek, E. Gramatová","doi":"10.1109/DDECS.2012.6219048","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219048","url":null,"abstract":"The paper is targeted to current and advanced technologies in education, mainly to electronic interactive education in the design and test fields. Nowadays, many different types of electronic systems exist for e-learning, m-learning, general electronic presentation systems for helping lecturers to make education more attractive and helpful for students. The electronic presentation systems offer teachers to prepare and present their educational materials in simpler way and allow presenting more information, figures and interesting documents for students. Such presentation systems are mainly helpful for teachers but presentation does not have to be attractive for students because they are not actively involved into the education. Current technologies offer Tablet PCs with new input - touch-screen display and stylus for writing some remarks into slides by hand. Both, teachers and students can use this input. But students are not still involved directly into the teaching process, thus a teacher has less information about students' knowledge. In addition, presentation systems are generally implemented in such way the teacher has to prepare all materials before its presentation. The paper presents a new interactive electronic presentation system for design and test of digital circuits. The developed system, named D&T Presenter allows integration of new methods into the education using interactive works with students based on on-line anonymous test and answer sheets during lectures. The presentation system was evaluated at the Slovak University of Technology in Bratislava during the course Testability of digital systems and shows very good and useful feedbacks from students.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"26 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134101924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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