2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献_第2页

LC-VCO design automation tool for nanometer CMOS technology 用于纳米CMOS技术的LC-VCO设计自动化工具

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219027

Krzysztof Siwiec, T. Borejko, W. Pleskacz

引用次数: 10

Reliability challenges in avionics due to silicon aging 硅老化对航空电子设备可靠性的挑战

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219085

B. Mesgarzadeh, I. Söderquist, A. Alvandpour

引用次数: 8

Fault management in an IEEE P1687 (IJTAG) environment IEEE P1687 (IJTAG)环境下的故障管理

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219013

E. Larsson, Konstantin Sibin

引用次数: 14

Generation of non-overlapping clock signals without using a feedback loop 产生不重叠的时钟信号，不使用反馈回路

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219061

R. Spilka, G. Hilber, Andreas Rauchenecker, D. Gruber, M. Sams, T. Ostermann

引用次数: 3

A gigabit fully integrated plastic optical fiber receiver for a RC-LED source 用于RC-LED光源的千兆完全集成塑料光纤接收器

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219028

M. Atef, R. Swoboda, H. Zimmermann

{"title":"A gigabit fully integrated plastic optical fiber receiver for a RC-LED source","authors":"M. Atef, R. Swoboda, H. Zimmermann","doi":"10.1109/DDECS.2012.6219028","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219028","url":null,"abstract":"The presented work describes a plastic optical fiber receiver for gigabit transmission using a resonant cavity light emitting diode (RC-LED). The integrated optical receiver is realized in 0.6μm BiCMOS technology. The main novelty of the presented design is the integration of the equalizer with the optical receiver. A large area Si photodiode is integrated with the optical receiver. The design combines a TIA, equalizer and post amplifier stage followed by a 50 Ω output driver. To minimize power supply noise and substrate noise, a fully differential design is used. A dummy TIA provides a symmetrical input signal reference and a control loop is used to compensate the offset levels. The total transimpedance of the complete receiver chain is in the range of 85dBΩ. The value of the DC gain and the corner frequency of the equalizer can be adapted via an external control voltage to adapt the design to different SI-POF lengths and RC-LED limited bandwidths. The optical receiver operates at a 3.3 V single power supply and the total current consumption is 31mA. The presented optical receiver succeeded to equalize the low-bandwidth transmission system (RC-LED and 50m POF). A data rate of 1Gbit/s can be transmitted over 50m SI-POF with a sensitivity of -13dBm at BER of 10-9.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115868334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Evaluation of susceptibility of FPGA-based circuits to fault injection attacks based on clock glitching 基于时钟故障的fpga电路对故障注入攻击的易感性评估

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219047

Jakub Korczyc, A. Krasniewski

引用次数: 8

On test time reduction using pattern overlapping, broadcasting and on-chip decompression 利用模式重叠、广播和片上解压缩减少测试时间

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219078

Martin Chloupek, O. Novák, Jiri Jenícek

引用次数: 14

A low phase noise Ka-band voltage controlled oscillator using 0.15 µm GaAs pHEMT technology 采用0.15µm GaAs pHEMT技术的低相位噪声ka波段压控振荡器

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219029

H. Kao, S. Shih, C. Yeh, Li-Chun Chang

引用次数: 3

Multisine signal generation method for a bioimpedance measurement device 一种生物阻抗测量装置的多正弦信号生成方法

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219035

M. Gorev, V. Pesonen, P. Ellervee

引用次数: 2

Design techniques for increasing performance and resource utilization of reconfigurable soft CPUs 提高可重构软cpu性能和资源利用率的设计技术

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219024

Alexander Wold, Dirk Koch, J. Tørresen

{"title":"Design techniques for increasing performance and resource utilization of reconfigurable soft CPUs","authors":"Alexander Wold, Dirk Koch, J. Tørresen","doi":"10.1109/DDECS.2012.6219024","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219024","url":null,"abstract":"Reconfigurable hardware allows application specific customization of soft microprocessors. Techniques such as removing unused instructions, software emulation of instructions, custom instruction set extensions, and run-time reconfigurable instructions have been suggested. However, the techniques have largely been studied separately from each other. The contribution of this paper is a classification method enabling integration of these techniques. This allows for generating an application specific microprocessor based system from a given program. The generated microprocessor is optimized with respect to performance per area. The improvement of our methodology is demonstrated for the CoreBench benchmark. The benefit of combining the removal of unused instructions (ISA subsetting) with software emulation of rarely used instructions is shown to increase performance while at the same time reducing resource requirements. Improvement in both area and performance is accomplished thorough simplifying the design allowing an increase in clock frequency for the synthesized soft CPU. Optimizing only by using custom instructions allowed a 12% increase in performance, but also increased resource usage by 6%. Software emulation combined with ISA subsetting allowed area savings of 7%, but only improved performance by 3%. By combining custom instructions, software emulation and ISA subsetting, we achieved an performance improvement of 15% while at the same time reducing resource requirements.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131696179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7