On test time reduction using pattern overlapping, broadcasting and on-chip decompression

Abstract

The paper deals with the problem of test data volume, test application time and on-chip test decompressor hardware overhead of scan based circuits. Broadcast-based test compression techniques can reduce both the test data volume and test application time. Pattern overlapping test compression techniques are proven to be highly effective in the test data volume reduction and low decompressor hardware requirements. This paper presents a new test compression and test application approach that combines both the test pattern overlapping technique and the test pattern broadcasting technique. This new technique significantly reduces test application time by utilizing a new on-chip test decompressor architecture presented in this paper.