2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献_第8页

Generation of SystemC/TLM code from UML/MARTE sequence diagrams for verification 从UML/MARTE序列图中生成SystemC/TLM代码以进行验证

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219051

E. Ebeid, D. Quaglia, F. Fummi

引用次数: 14

CIVA: Custom instruction vulnerability analysis framework CIVA:自定义指令漏洞分析框架

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219081

A. Azarpeyvand, M. Salehi, S. M. Fakhraie

引用次数: 9

Differential evolutionary optimization algorithm applied to ESD MOSFET model fitting problem 差分进化优化算法应用于ESD MOSFET模型拟合问题

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219043

Tomas Napravnik, V. Kote, V. Molata, J. Jakovenko

引用次数: 1

Design and implementation of high-performance high-valency ling adders 高性能高频加法器的设计与实现

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219062

T. Koçak, Preeti S. Patil

引用次数: 2

Automatic integration of hardware descriptions into system-level models 将硬件描述自动集成到系统级模型中

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219034

Ralph Görgen, Jan-Hendrik Oetjens, W. Nebel

引用次数: 6

BTI impact on logical gates in nano-scale CMOS technology BTI对纳米级CMOS技术中逻辑门的影响

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219086

Seyab Khan, S. Hamdioui, H. Kukner, P. Raghavan, F. Catthoor

{"title":"BTI impact on logical gates in nano-scale CMOS technology","authors":"Seyab Khan, S. Hamdioui, H. Kukner, P. Raghavan, F. Catthoor","doi":"10.1109/DDECS.2012.6219086","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219086","url":null,"abstract":"As semiconductor manufacturing has entered into the nanoscale era, Bias Temperature Instability (BTI) -Negative BTI (NBTI) in PMOS transistors and Positive BTI (PBTI) in NMOS transistors- has become one of the most serious aging mechanisms that reduces reliability of logic gates. This paper presents a simulation-based BTI analysis in both basic (such as NAND and NOR) and complex gates while considering the impact of input's duty cycle, the frequency at which they change, as well as the impact of the stressed transistor location. The simulation results show that the impact of BTI is strongly gate dependent and that in general the impact in complex gates is larger. When considering both NBTI and PBTI for basic gates, the results reveal that for a NOR gate the impact of NBTI is 2.19× higher than that of PBTI; while for a NAND gate, PBTI impact is 1.27× higher than that of NBTI. When considering different input duty cycles and their frequencies, the results show that the higher the duty cycle, the lower NBTI impact and the higher the PBTI impact regardless of the gate types and the frequency; a variation of ±30% duty cycle causes a variation of up to 49% variation in the impact of NBTI and a variation of 16% in the impact of PBTI. For complex gates, the results show similar trends, but with higher impact.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128254955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 48

Efficient link-level error resilience in 3D NoCs 三维noc中有效的链路级错误恢复能力

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219038

V. Pasca, S. Rehman, L. Anghel, M. Benabdenbi

引用次数: 3

Test and configuration architecture of a sub-THz CMOS detector array 次太赫兹CMOS探测器阵列的测试与配置架构

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219033

P. Földesy, D. Gergelyi, C. Fuzy, G. Károlyi

引用次数: 6

AGATE - towards designing a low-power chip multithreading processor for mobile software defined radio systems AGATE -为移动软件无线电系统设计一种低功耗芯片多线程处理器

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219018

Krzysztof Marcinek, W. Pleskacz

{"title":"AGATE - towards designing a low-power chip multithreading processor for mobile software defined radio systems","authors":"Krzysztof Marcinek, W. Pleskacz","doi":"10.1109/DDECS.2012.6219018","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219018","url":null,"abstract":"Providing low power consumption, high throughput and flexible solution is a challenge during designing process of a mobile software defined radio (SDR) system. The need for simple software generation using common programming tools becomes also a very significant factor. The paper presents the design and implementation of a chip multithreading general-purpose processor core (GPP), as the first step towards designing a flexible and programmer friendly SDR processor platform. Software tools developed for the hardware are described. The future work will be focused on designing tightly-coupled coprocessor extensions (TCC) for an application specific digital signal processing (DSP) purposes. AGATE processor system is described in form of a highly configurable library using Verilog language. The concept verification process was performed on the Xilinx Virtex-6 ML605 FPGA evaluation board. The maximum achieved frequency for the 8-thread processor is 190 MHz. Gate level simulation along with Value Change Dump (VCD) power estimation analysis were performed using three CMOS technologies: 130 nm, 90 nm and 65 nm. AGATE is capable of performing up to 0.72 DMIPS/MHz/thread with the maximum frequency of over 700 MHz and the power consumption of about 3 mW/core using 65 nm process.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121870344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Asynchronous circuit design: From basics to practical applications 异步电路设计:从基础到实际应用

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-01 DOI: 10.1109/DDECS.2012.6219011

E. Grass, M. Krstic, Xin Fan, Steffen Zeidler

引用次数: 0