2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献_第3页

Reduction of complex safety models based on Markov chains 基于马尔可夫链的复杂安全模型约简

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219050

Martin Kohlík, H. Kubátová

引用次数: 1

Low power scan by partitioning and scan hold 低功耗扫描分区和扫描保持

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219070

Efi Arvaniti, Y. Tsiatouhas

引用次数: 15

An automated infrastructure for real-time monitoring of multi-core Systems-on-Chip 用于实时监控多核片上系统的自动化基础设施

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219025

Georgios Kornaros, I. Christoforakis, M. Astrinaki

{"title":"An automated infrastructure for real-time monitoring of multi-core Systems-on-Chip","authors":"Georgios Kornaros, I. Christoforakis, M. Astrinaki","doi":"10.1109/DDECS.2012.6219025","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219025","url":null,"abstract":"Requirements for rapid turnaround development of complex multi-core Systems-on-Chip nowadays have advanced to the level at which a number of different in principle validation techniques have to be performed in short time. Quite common are hybrids of passive debugging of Systems-on-Chip and event-driven active verification. On top of these, we present a novel highly flexible verification infrastructure, in which parameters of monitoring can be accessible in real-time while the measurement itself is being performed. Instead of simply observing components under development, the proposed infrastructure enables the designer to interact, monitor and adjust in real-time system parameters or application software. This paper explores different microarchitecture alternatives to efficiently support flexible real-time monitoring via hardware configurable monitors which can provide abstractions of the information. A quantitative evaluation of the proposed methodology on a system-on-FPGA provides results that can serve as guidelines for system-level designers, proving the need for flexible and at the same time efficient filters for real-time monitors inside complex multi-core SoCs.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114281536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A simulation framework for 3-dimension Networks-on-chip with different vertical channel density configurations 具有不同垂直通道密度配置的三维片上网络仿真框架

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219030

Haoyuan Ying, A. Jaiswal, Mohamed A. Abd El-Ghany, T. Hollstein, K. Hofmann

{"title":"A simulation framework for 3-dimension Networks-on-chip with different vertical channel density configurations","authors":"Haoyuan Ying, A. Jaiswal, Mohamed A. Abd El-Ghany, T. Hollstein, K. Hofmann","doi":"10.1109/DDECS.2012.6219030","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219030","url":null,"abstract":"3D ICs are emerging as a promising solution for scalability, power and performance demands of next generation Systems-on-Chip (SoCs). Along with the advantages, it also imposes a number of challenges with respect to cost, technological reliability, thermal budget and so forth. Networks-on-chip (NoCs), which is thoroughly investigated in 2D SoCs design as scalable interconnects, is also well relevant to 3D IC Design. The cost of moving from 2D to 3D should be justified with improvements in performance, power or latency. To solve this problem, this paper presents a new simulation framework for 3D NoCs. We established a new Generic Scalable Pseudo Application (GSPA), where user can generate their own scalable pseudo applications. We have also integrated the state-of-the-art benchmarks to evaluate the 3D NoC system. In the framework, the 3D NoC with different vertical channel densities (VD) (i.e. number of Through-Silicon-Vias (TSVs)) can be generated according to the preference of users. After the simulation, the power consumption and system performance are evaluated. We have compared 2D NoC architecture with 3D NoC architecture with different VDs. The experimental results show that 3D architectures have significant advantage (Avg. 51%, 44%, 35% for 100%, 50%, 25% VD, respectively) in the aspect of interconnect power delay product in comparison to 2D mesh architecture. The 25% VD architecture is the best choice with 17% advantage over full connection (100% VD) 3D NoC architecture in the aspect of Figure of Merit which takes area and TSV connection yield into account among all the experiments for the given constrains.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114323937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

High speed FPGA implementation of hough transform for real-time applications 高速FPGA实现霍夫变换的实时应用

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219060

L. Voudouris, S. Nikolaidis, A. Rjoub

引用次数: 3

Automated synthesis and design-error repair of systems 系统的自动合成和设计错误修复

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219012

Georg Hofferek

引用次数: 0

Multiple stuck-at-fault detection theorem 多重故障卡检定理

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219064

R. Ubar, S. Kostin, J. Raik

引用次数: 16

The design of dependable flexible multi-sensory System-on-Chips for security applications 为安全应用设计可靠灵活的多传感器片上系统

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219039

H. Kerkhoff, Yong Zhao

引用次数: 3

Auto-calibration techniques in built-in jitter measurement circuit 内置抖动测量电路中的自动校准技术

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219066

Chih-Ping Cheng, Jen-Chieh Liu, Kuo-Hsing Cheng

引用次数: 1

Automated debugging from pre-silicon to post-silicon 从预硅到后硅的自动调试

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/ddecs.2012.6219082

M. Dehbashi, G. Fey

引用次数: 10