Automated synthesis and design-error repair of systems

Abstract

Due to the ever increasing complexity of digital systems, the need for formal verification methods has also been increasing steadily. Verification usually requires some form of specification. Having available a formal specification for a system, one can ask why designers have to bother fixing errors that have been detected. Or, going one step further, why not synthesize the entire system from the specification? We will have a look at two state-of-the-art automated and correct-by-construction synthesis methods that address these questions. First, we will consider property synthesis, which can be viewed as a game. Second, we show how to benefit from abstraction by uninterpreted functions.