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2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献

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Design methodology for fault tolerant ASICs 容错专用集成电路的设计方法
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219014
V. Petrovic, M. Ilic, G. Schoof, Z. Stamenkovic
{"title":"Design methodology for fault tolerant ASICs","authors":"V. Petrovic, M. Ilic, G. Schoof, Z. Stamenkovic","doi":"10.1109/DDECS.2012.6219014","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219014","url":null,"abstract":"The sensitivity of application specific integrated circuits (ASICs) to the single event effects (SEE) can induce failures of the systems which are exposed to increased radiation levels in the space and on the ground. This paper presents a design methodology for a full fault tolerant ASIC that is immune to the single event upsets (SEU) in sequential logic, the single event transients (SET) in combinational logic and the single event latchup (SEL). The dual modular redundancy (DMR) and a SEL power-switch (SPS) are the basis for a modified ASIC design flow. Measurement results have proven the correct functionality of DMR and SPS circuits, as well as a high fault tolerance of implemented ASICs along with moderate overhead in respect of power consumption and occupied silicon area.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129494337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A low voltage sigma delta modulator for temperature sensor 一种用于温度传感器的低压σ δ调制器
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219072
Yi-Hsiang Juan, C. Luo, Hong-Yi Huang
{"title":"A low voltage sigma delta modulator for temperature sensor","authors":"Yi-Hsiang Juan, C. Luo, Hong-Yi Huang","doi":"10.1109/DDECS.2012.6219072","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219072","url":null,"abstract":"A sigma delta modulator is proposed to transform the analog front end of temperature sensor to digital signal. By adding additional poles and altering the zero of the transfer function, the SNR and dynamic range can be enhanced. The chopper stabilization scheme is included to reduce the DC offset and 1/f noise. A low voltage circuitry is invented to reduce the power consumption. The circuit is simulated using a 0.18μm 1p6m CMOS process with a signal bandwidth of 40Hz and oversampling ratio (OSR) of 64. The post-layout simulations of a test chip show 70dB SNR, 78dB dynamic range and 12.6 bits ENOB. The power dissipation is 32 μW at a 1-V supply voltage and the core area is 0.445 × 0.675 mm2.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134219920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
OBIST strategy versus parametric test - Efficiency in covering catastrophic faults in active analog filters OBIST策略与参数测试——有源模拟滤波器中覆盖灾难性故障的效率
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219053
D. Arbet, G. Gyepes, J. Brenkus, V. Stopjaková
{"title":"OBIST strategy versus parametric test - Efficiency in covering catastrophic faults in active analog filters","authors":"D. Arbet, G. Gyepes, J. Brenkus, V. Stopjaková","doi":"10.1109/DDECS.2012.6219053","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219053","url":null,"abstract":"This paper deals with the comparison of the fault coverage of catastrophic faults in active analog integrated filter obtained by the measurement of filter parameters and by the Oscillation-based Built-In Self Test (OBIST) approach. In our experiment, firstly, the cut-off frequency, ripple in the pass band, DC gain in pass band and group delay of the filters have been monitored in the operating mode. Then, during the test mode (OBIST), the filter is transformed to an oscillator, and the oscillation frequency is compared to the frequency from a dedicated on-chip reference oscillator to compensate undesired influence of technology variations. The obtained results on the efficiency of both approaches are compared.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133029363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Bounded model checking of Contiki applications contki应用的有界模型检验
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219069
T. Vörtler, Steffen Rülke, P. Hofstedt
{"title":"Bounded model checking of Contiki applications","authors":"T. Vörtler, Steffen Rülke, P. Hofstedt","doi":"10.1109/DDECS.2012.6219069","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219069","url":null,"abstract":"Verification of embedded systems is a challenge due to the tight combination of hardware and software. We present an approach on the automatic verification of embedded system applications for the operating system Contiki using a standard bounded model checking tool for software. By using an operating system a higher abstraction level to hardware is possible. Our approach is therefore easily applicable for the verification of different hardware platforms.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133387319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Combining on-line fault detection and logic self repair 结合在线故障检测和逻辑自修复
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219076
T. Koal, Markus Ulbricht, H. Vierhaus
{"title":"Combining on-line fault detection and logic self repair","authors":"T. Koal, Markus Ulbricht, H. Vierhaus","doi":"10.1109/DDECS.2012.6219076","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219076","url":null,"abstract":"In recent years many authors have addressed the growing vulnerability of nano-electronic circuits and systems to transient faults and wear-out effects. Hence present and even more future electronic systems need the property of resilience against different types of fault effects for long-term dependable operation. Fault detection, error compensation, and also repair technologies require a substantial overhead in extra hardware resources, which add to system size, cost and power consumption. In this paper we present a first attempt to combine resources for transient fault handling and for permanent fault repair in a unified approach.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134261838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An adaptive self-test routine for in-field diagnosis of permanent faults in simple RISC cores 一种用于简单RISC内核永久故障现场诊断的自适应自检程序
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219080
Mario Schölzel, T. Koal, H. Vierhaus
{"title":"An adaptive self-test routine for in-field diagnosis of permanent faults in simple RISC cores","authors":"Mario Schölzel, T. Koal, H. Vierhaus","doi":"10.1109/DDECS.2012.6219080","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219080","url":null,"abstract":"The localization of permanent faults in a processor is a precondition for applying (self-)repair functions to that processor core. This paper presents a software-based self-test technique that can be used in the field for test and fault localization, there-by providing a high diagnostic resolution. It is shown how the self-test routine is adapted in the field to already detected faults in the processor, such that these faults do not affect the test- and diagnostic capability of the self-test routine. By this it becomes reasonable to localize multiple permanent faults in the processor. The proposed self-test is software-based, but it requires a few modifications of the processor. The feasibility of the technique is presented by an example; limitations are discussed, too.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121800101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
CDMA technique for Network-on-Chip 片上网络的CDMA技术
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219045
A. Badry, Mohamed A. Abd El-Ghany
{"title":"CDMA technique for Network-on-Chip","authors":"A. Badry, Mohamed A. Abd El-Ghany","doi":"10.1109/DDECS.2012.6219045","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219045","url":null,"abstract":"A Code-Division Multiple Access (CDMA) based on-chip communication network is proposed in this paper. The proposed design features a novel encoding and decoding scheme for CDMA transmission which improves area, latency and power dissipation of the network on Chip (NoC). The orthogonal and balance properties of Walsh codes are used for the routing of data between the resources on the network. The proposed CDMA encoding and decoding schemes are compared with the conventional schemes. The overall area required to implement the proposed CDMA NoC design is reduced by 54%. The design decreases the latency of the network by 48.2%. The total power consumption required to achieve the proposed design is decreased by 54.8%.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127929511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Online self-checking and correction for crosstalk-induced timing errors on VLSI interconnects VLSI互连串扰时序误差的在线自检与校正
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219077
Ping-Liang Lai, Der-Chen Huang
{"title":"Online self-checking and correction for crosstalk-induced timing errors on VLSI interconnects","authors":"Ping-Liang Lai, Der-Chen Huang","doi":"10.1109/DDECS.2012.6219077","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219077","url":null,"abstract":"In this paper, a two-phase study was accomplished to explore the error identification and classification in terms of designing a self-check and correction circuit for crosstalk timing errors. A signature fault model (SFM) was firstly derived from an error space and a logical signature model (LSM) to recovery crosstalk timing errors such as glitch, delay, and speedup. Second, a transistor-level error detector, called crosstalk- error self-repairer (CESR), was designed to simplify the proposed SFM model. The proposed circuit has the capability of online error detection, correction, and error tolerant to obtain more reliable on-chip communication. In addition, the experimental results had been conducted thoroughly to demonstrate the effectiveness of our proposed work.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129981553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
System side-channel leakage emulation for HW/SW security coverification of MPSoCs mpsoc硬件/软件安全防护的系统侧信道泄漏仿真
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219040
Armin Krieg, J. Grinschgl, C. Steger, R. Weiss, H. Bock, J. Haid
{"title":"System side-channel leakage emulation for HW/SW security coverification of MPSoCs","authors":"Armin Krieg, J. Grinschgl, C. Steger, R. Weiss, H. Bock, J. Haid","doi":"10.1109/DDECS.2012.6219040","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219040","url":null,"abstract":"During recent years a tremendous number of embedded systems has been introduced into every person's house-hold. Such systems cannot only be found inside non-critical applications like entertainment devices but also in safety or security critical implementations like smart-cards. The increasing complexity leads to the introduction of several different co-design techniques to enable the parallel design of the system's hardware and software. Especially concerning security evaluation procedures this may raise a problem of trust between the manufacturer of the hardware and the software if both are different entities. To enable a bridge between these two worlds, simulation and emulation-based approaches have been shown in literature and industry to provide abstracted information about fault-attack effects to the software developer. However, no fast and cost-effective approach is available to provide a metric about how much of a given secret is leaking from the device to its environment. Therefore, this paper proposes such a metric and an emulation-based methodology to enable an early estimation of side-channel leakage to a possible adversary. The effectiveness of our approach is shown using a common available system-on-chip implementation using an open-source standard-cell library for characterization and a FPGA-based emulation platform for demonstration.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130142475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A low-overhead monitoring ring interconnect for MPSoC parameter optimization 一种用于MPSoC参数优化的低开销监测环互连
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI: 10.1109/DDECS.2012.6219023
Abdelmajid Bouajila, Abdallah Lakhtel, Johannes Zeppenfeld, W. Stechele, A. Herkersdorf
{"title":"A low-overhead monitoring ring interconnect for MPSoC parameter optimization","authors":"Abdelmajid Bouajila, Abdallah Lakhtel, Johannes Zeppenfeld, W. Stechele, A. Herkersdorf","doi":"10.1109/DDECS.2012.6219023","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219023","url":null,"abstract":"MPSoCs need to integrate self-x properties in order to get rid of the worst-case design style which is no longer affordable in large SoCs. Integrating self-x properties in SoCs is possible through a monitoring interconnect which carries monitor information to evaluators that decide on actions that will tune the SoC operation mode. We have designed a customized interconnect for SoC monitoring/actuation. We have implemented it in VHDL and tested it in FPGA. The prototype proved that this customized interconnect provides good results regarding latency and area overheads and is a key component in enabling self-optimization in our FPGA MPSoC prototype.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124389315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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