Online self-checking and correction for crosstalk-induced timing errors on VLSI interconnects

Abstract

In this paper, a two-phase study was accomplished to explore the error identification and classification in terms of designing a self-check and correction circuit for crosstalk timing errors. A signature fault model (SFM) was firstly derived from an error space and a logical signature model (LSM) to recovery crosstalk timing errors such as glitch, delay, and speedup. Second, a transistor-level error detector, called crosstalk- error self-repairer (CESR), was designed to simplify the proposed SFM model. The proposed circuit has the capability of online error detection, correction, and error tolerant to obtain more reliable on-chip communication. In addition, the experimental results had been conducted thoroughly to demonstrate the effectiveness of our proposed work.