{"title":"多重故障卡检定理","authors":"R. Ubar, S. Kostin, J. Raik","doi":"10.1109/DDECS.2012.6219064","DOIUrl":null,"url":null,"abstract":"The paper discusses the problem of testing multiple faults in combinational circuits. A definition of a test group is introduced for easier handling of fault masking. Test pair, as a known concept for proving correctness of a line in the circuit is regarded as a special case of the test group. A theorem is proved that if the test group will pass then a particular sub-circuit can be regarded as fault free at any possible combination of stuck-at-faults (SAF) in the circuit. Unlike the traditional approaches, we do not target the faults as test objectives. The goal is to verify the correctness of a part of the circuit. The whole test sequence is presented as a set of test groups where each group has the goal to identify the correctness of a selected part of a circuit.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Multiple stuck-at-fault detection theorem\",\"authors\":\"R. Ubar, S. Kostin, J. Raik\",\"doi\":\"10.1109/DDECS.2012.6219064\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper discusses the problem of testing multiple faults in combinational circuits. A definition of a test group is introduced for easier handling of fault masking. Test pair, as a known concept for proving correctness of a line in the circuit is regarded as a special case of the test group. A theorem is proved that if the test group will pass then a particular sub-circuit can be regarded as fault free at any possible combination of stuck-at-faults (SAF) in the circuit. Unlike the traditional approaches, we do not target the faults as test objectives. The goal is to verify the correctness of a part of the circuit. The whole test sequence is presented as a set of test groups where each group has the goal to identify the correctness of a selected part of a circuit.\",\"PeriodicalId\":131623,\"journal\":{\"name\":\"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-04-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DDECS.2012.6219064\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2012.6219064","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The paper discusses the problem of testing multiple faults in combinational circuits. A definition of a test group is introduced for easier handling of fault masking. Test pair, as a known concept for proving correctness of a line in the circuit is regarded as a special case of the test group. A theorem is proved that if the test group will pass then a particular sub-circuit can be regarded as fault free at any possible combination of stuck-at-faults (SAF) in the circuit. Unlike the traditional approaches, we do not target the faults as test objectives. The goal is to verify the correctness of a part of the circuit. The whole test sequence is presented as a set of test groups where each group has the goal to identify the correctness of a selected part of a circuit.